Design Of Adaptive Low Leakage SRAM At 40nm Process

The density of internal transistors in SRAM is high,and the proportion of SRAM in the area of the SoC chip is high,resulting in the leakage current of SRAM becoming the main part of the leakage current of SoC chip.For Io T chips that often need to enter sleep mode,the static energy loss in the sleep mode may be higher than the dynamic energy loss in the active mode,and reducing SRAM leakage current can effectively save chip energy consumption.Reducing the supply voltage of SRAM during sleep mode can reduce the leakage current of SRAM under different temperatures and process conditions,but the supply voltage cannot be reduced without limit,otherwise the data retention yield of SRAM cannot be guaranteed,so it needs to be adjusted according to the minimum data retention voltage of SRAM.This thesis takes ±6δ yield as the design requirement,firstly analyzes the effect of sub-threshold channel current on the minimum data retention voltage,and secondly analyzes the effect of gate leakage current caused by the gate oxide layer on the minimum data retention voltage of SRAM under extreme process fluctuations.It was finally found that under the same process conditions,the minimum data retention voltage of the 40 nm process SRAM decreased with increasing temperature;at the same temperature,the minimum data retention voltage of the SS,TT,and FF process conditions decreased sequentially.According to this phenomenon,this thesis designs a reference voltage generation module based on the sub-threshold region,monitors the temperature and process conditions,and adjusts the supply voltage of the SRAM in the sleep mode according to the output of the reference voltage generation module by closed-loop feedback adjustment to reduce SRAM leakage current under different temperature and process conditions.In this thesis,a low leakage SRAM with a capacity of 16 KB is designed based on the 40 nm process.Compared with SRAM provided by semiconductor foundry under the same process,at 25℃,the leakage current of the SRAM under SS,TT,and FF process conditions is reduced by 56%、59.8%、37%,at 100℃,the leakage current of SS,TT,FF process conditions were reduced by 74.5%、38.7%、35%.