New 10T Cell Of Research And Low Power SRAM Design Based On 40nm Process

With the rapid development of SOC technology,all kinds of the battery power supply of portable electronic products has been widely used,such as smart phones,hand ring,the device,such as part of the automobile electronic.In recent years,semiconductor technology has entered the stage of deep sub-micron and nanometer,craft size shrinking,but due to the slow development of battery technology and chip cooling technology is imperfect and so on lead to power consumption has become an important problemSOC urgently needs to solve.While SRAM is an important part in SOC,and the proportion of the total area of the chip is more and more big.The power consumption of the chip directly affects the life of the battery,as a result,research a SRAM low-power technology has a strong practical significance.At first,this paper analyses the power source of SRAM and a common way to reduce the power consumption of the SRAM.SRAM power source mainly includes three parts: the dynamic power consumption,static power consumption,short circuit power consumption.Power consumption and power supply voltage has a direct relationship,dynamic power consumption and power supply voltage into a quadratic relationship,static power consumption,short circuit power consumption and power supply voltage in a power relationship,thus reduce the supply voltage can bring an SRAM substantially reduce power consumption.Storage unit in the power supply voltage of the traditional 6T SRAM cell reduce reliability variation occurs,lacking the ability to write,read and write and even wrong defects,this paper designed a new 10 T cell SRAM,unique circuit structure determines it works under low supply voltage.To illustrate the performance of the 10 T cell,the various parameters of it under different PVT have carried on the simulation analysis.The parameters are SNM,WM,Readcurrent,Leakage and Max WL.In this paper,according to the characteristics of the 10 T cell SRAM,we design the corresponding peripheral circuits,including sequential control circuits,the sensitive amplifier circuit,decoding circuit,Tracking circuit,etc.,and set up a 16 x16 1024 Kb SRAMunder the SMIC 40 nm process.Through the simulation of SRAM,verified the accuracy of its function,after we reduce the supply voltage of SRAM,and adjust the corresponding clock frequency,the simulation analysis of this paper designed an SRAM minimum working voltage of 0.5 V,the clock frequency of 500 KHZ,based on TT corner and the temperature is 25?,reading power consumption is 0.371 uW,writing power consumption is 0.334 uW,static power consumption is 0.115 uW,implements the power supply voltage of the greatly reduced,thus make SRAM have significantly reduce power consumption,achieving the target of the design of low power SRAM.