The Design And Implementation Of High Speed SRAM In L1 Cache Tag Under 65nm Process

The design of L1 Cache is essential in high-performance microprocessor, as its access speed directly limits the microprocessor's performance. Cache tag array is usually implemented by SRAM (static random access memory),which is required to fulfill store and load operations in single cycle. Therefore, high-speed and high-reliability design of SRAM is an important goal.This module is a part of X microprocessor developed by National University of Defense Technology in this dissertation . Using 65nm technology, the work is required to reach 1.5 GHz. As L1 Cache memory access time is a bottleneck in processor performance, it needs full custom design to implement. From this point of view, the paper achieve the design of 15k's High-speed SRAM.The main results of this paper is as follows: The first, as special timing requirements of shared decoding during read and write operations are needed, three schemes are proposed and finally a reasonable one is selected. The Second, a novel partition method of array is proposed in this research. The main consideration is speed priority principle and acess reliability in 65nm process. The third , in this paper we analyse the problem of reliablity with threshold change caused by random doping under 65nm process, which can cause failure to read and write. Therefore, it should be considered accordingly. The dissertation introduces some industry solutions to the problem, and a new solution has been concluded. The forth, SRAM usually improves the access speed by external circuit design optimized. These techniques are more mature currently. Employing high reliability circuit, we construct a series of high-performance and high reliability external circuits by logic optimization and array division in this dissertaion.We achieve the following flow in this dissertation: requirement analysis - circuits design– layout design - simulation and verification. The result shows the function is correct. The worst result shows that the delay of read and write is 334ps and 332.4ps, respectively, compared with SRAM Compiler under the same process. The access time is shortened by 53%, which meets the design requirements.