Full Custom Design And Realization Of SRAM In L2 Cache Tag

With the development of the microelectronics and the progress of the process technology, the performance of processors is improved, and the area proportion of SRAM in processor is growing gradually. It is estimated that in 2010, 90% of the area in a processor will be occupied by different memories. In the recent years, the popularity of portable devices and the need of high performance processors, higher performance SRAMs are required. Higher performance and lower power consumption are becoming the main stream of SRAM designs. To design SRAM with high speed, low power, small area and high reliability is the optimal target.In the high performance micro processor, SRAM adopted by cache memory has seriously restricted advancement of the micro processor. Now, SRAM can be designed using full-custom, which can improve the performance of SRAM and overcome the bottle-neck problem induced by unmatchable speed when micro processor access to the cache memory. However, as CMOS feature size decreases, the width of the interconnection will reduce. So the delay of the interconnection that has been avoided in former designs becomes to various problems. The very thin gate-oxidation induces supply voltage scaling continuously. For speed of the chip, the threshold voltage has to reduce. Because it is reverse- exponential relation between sub-threshold current and threshold voltage, so the threshold leakage power has been the most various problem in the CMOS design.Based on research of the present problem, we design a SRAM under the process of 0.13μm CMOS with full custom. The full flow includes logic design, layout design, BIST design and verification after sign off. In the work, SRAM is designed with multi-bank partitions. In order to improve the SRAM performance, the critical paths are optimized through multi-level decoding, sense amplifier and comparing circuit optimizing. Simulation results indicate that read/write performance and power consumption of the SRAM designed in this paper have improved greatly. Among them, the delay of data storing is less than 798ps, the delay of data loading is less than 983ps, and the power consumption of access is 23.286mW. Compared with the SRAM designed with memory compiler under the same technology, the access time reduces by 20% and the average power consumption reduces by 10%.