The Full Custom Design Of High Speed Low Power SRAM Under 65nm Process

The design of L1 Cache is essential in high-performance microprocessor, as itsaccess speed directly limits the microprocessor's performance. Cache tag array isusually implemented by SRAM (static random access memory),which is required tofulfill store and load operations in single cycle. Therefore, high-speed andhigh-reliability design of SRAM is an important goal. The SRAM has beenimplemented in 65nm CMOS process. It has 2-read and 2-write ports,. The size is512-word×28-bit. The simulation results indicate: the read delay is 344.3ps, the writedelay is 310.0ps, and the clock frequency is up to 2GHz. Comparing with the synthesisresult of half-custom design, the clock frequency increased from 1GHz to 2GHz, whichis optimized nearly 1 times, and the area reduced from 83285.79μm2 to less than63879.43μm2, which is optimized nearly 23%, and the power is also improved by theapplication of Low-power design methods and improve the application of low-powersense amplifier. They all achieve the design aim.The thesis mostly aims at high speed and low power. The main factors which affectthe Register File's speed have been optimized, and Low-power design techniques,Themain results of this paper is as follows:1. Since the SRAM is a 512k×28bit, two-stage decoding structure to parallelimplementation to speed up read and write speed of decoding, thus improving theperformance of the entire circuit.2. SRAM design optimization is usually through the external circuit to improve theliteracy rate, at present these technologies have a more mature, this low powerconsumption, fast readout sense amplifier design and an array of methods to increase bythe speed of the primary means of reading , the use of high reliability circuit stability,building a series of high-performance, low power consumption, high reliability externalcircuit.3. The paper, by full-custom design techniques, the use of hierarchical full-customdesign method and layout of the plan to divide the territory, reducing the size of theterritory of about 23%.