The Design And Implementation Of High-Performance TPSRAM In 40nm Process

Static Random Memory(SRAM) is mainly used to system caches in high-performance microprocessor. These instructions and data needed for processor are kept in the first level cache, the SRAM used for the first level cache is required to be high speed as well as small memory capacity.Facing with the behavioral requirement of the first level cache, the paper focuses on the design of TPSRAM with small capacity and high performance, we usually called the memory designed by the 8 Tube SRAM cell for TPSRAM. Application of TPSRAM in a variety of YHFT-X DSP chip, and can meet the requirements of 1G Hz frequency.The high performance of memory is reflected in Circuit Design and Layout Design. SRAM is devided into Clock module, Latch module, Decoder module, Storage module and I/O module five modules, respectively, to carry on the design. In this paper, the design is embodied in two aspects of Circuit Design and Layout Design.1) SRAM Circuit DesignIn the Clock module, the gated logic cell is used to generate the gated clock signal, which decreases the unnecessary flip to reduce power consumption of the circuit losses. Take the signal obtained by reading the gated clock as the input signal caused by the circuit which was generated by narrow pulse, adjust the enough width of the narrow pulse until the GRBL(Final Read-Bit-Line) can be latched. It not only reduce the delay cells using of the narrow pulse circuit, but also decrease the GRBL delay through the trigger.In the Decoder module, using the secondary decoding circuit of the static CMOS logic, which can get higher stability and lower power consumption than dynamic decoding circuit.In the Storage module, 8T SRAM cell is the main part of storage arrays, which is better than traditional 6T SRAM cell in the aspect of stability, leakage current, area, power consumption and delay in 40 nm process. It plays an important part in improving the whole performance of the memory.In I/O module, The dynamic prefilled method is adopted in I/O module, data 0/1 is transmitted to GRBL through two paths respectively. Then GRBL is latched by the narrow pulse SR trigger, which make this part of the circuit has high speed, good stability and small area.2) SRAM Layout DesignThe strategy of bilateral symmetry floorplan and routing is used in SRAM Layout, which make the SRAM Layout more reasonable, the wire for routing becomes more shorter. This can improve the speed, stability and reduce the layout area in physical design.First, evaluate the memory performance to know the internal performance of the memory. Then by comparing with Semi-Custom design and Memory Compiler design, it can be found that the Full-Custom design’s area is 74% smaller, delay is 18% smaller, power consumption is 35% lower than the Semi-Custom design; the Full-Custom design’s area is 40% smaller, delay is 35% shorter, power consumption is 55% smaller than Memory Compiler design.