A Security SRAM Against Data Remanence Attack With Full Custom Design

With the development of VLSI and the information security is paid attention to more and more, the designs of the security system develop from the software to the hardware gradually. As a kind of volatile memory storage, SRAM is widely applied to involving in the occasion of information security. It is regarded as the memorizer of the key in a lot of security systems. It has a data remanence when it is power-off, which may cause information to be stolen. The experiment results show that, the data can be kept for 0.5~2 minutes at -30℃after power off, moreover, as chip size is smaller the data remanence is longer. It is important to research on data remanence in deep sub-micron SRAM and design security SRAM against data remanence attack.At first, the physical mechanism of data remanence in SRAM is discussed. Then the technology of data remanence attacked at low temperature and the defense tactics is discussed. Through analysis, a solution with data erasure strategy against data remanence attack is proposed, that is erasing the data through a special circuit when attack is detected on the chip. Combining this scheme, to the characteristics of data remanence, a SRAM cell structure with data erasure transistor is designed and implemented, which read line and write line are separated. Progressive erase control method is proposed according to its work characteristics. Designed and implemented a delay erase control circuit. In order to improve the performance of the proposed SRAM and improve stability and reduce the power consumption, the critical paths are optimized through using multi-level decoding, improved sense amplifier, improved precharge circuit etc. Finally, the layout plan, the basic cell design and the verification and simulation of the layout are discussed in this paper.in this paper,a 16kb(512×32bit) SRAM against data remanence attack is designed in 65nm CMOS process using full custom design method. The simulation results show that the design has succeeded in realizing the design object obviously. The final layout area of the proposed SRAM is 0.079mm~2 and the area used in data erase design is account for 21.27%. When operating frequency is 1GHZ and at room temperature, the delay of data writing is less than 599ps, the delay of data reading is less than 698ps, and the average power consumption is 4.74mW.