Full Custom Design And Realization Of High-Performance Memory Of X Processor

The X microprocessor is high-performance processor for efficient execution of stream application. It integrates many different kinds of memory units such as LRF, CCRF and SRF. In this dissertation, we focus our study on the full-custom design and implementation of these memory units, and employ a combined design methods to complete the implementation of a 32-word 65-bit register file with one read port and one write port, as well as a 2k-word 64-bit single port SRAM. The worst-case simulation results showed an operation time, both read and write operation, of less than 650ps in register file and less than 1.4ns in SRAM.Decoder is one of the most important components in a memory unit, and its improvement can greatly diminish the access time of both register file and SRAM. We combine a p-type dynamic circuit with a static decoder to solve the write-overlap problem in static decoder, and promote the decoding speed. Besides, with a good study of the circuit characteristics of decoder, we propose a gate skew technology to optimize the critical datapath. We apply both two methods in the design of SRAM decoder and achieve a satisfying result.A good floor plan in layout can efficiently reduce the area, energy and transition time of a circuit. While Euler Path is a solution to the floor plan of Compementy CMOS circuit layout, it is incapable to non-complementry CMOS circurt or CMOS circuit with none Euler path. In this dissertation, we present an expanded Euler Path method, which extend the origin Euler Path method to the floor plan of all kind of CMOS circuit as well as the dynamic circuit. We also apply this method in the floor plan of register file and SRAM layout, and gain a good result.