The Design Of Near-threshold Adiabatic SRAM

The cache occupies more than half of the high-performance microprocessor transistors, and cache is usually accomplished by SRAM(Static random Access Memory). SRAM design has been a hotspot in the semiconductor industry. The reliability and energy consumption are two major issues of concern to SRAM design, which meet the demand of the low-power design and high-reliability design in the development direction of IC design. Large capacity bus is usually contained in the SRAM, and frequently visited. It will consume a lot of power, thus the demand of low-power SRAM is increasing.Dynamic power occupies a large proportion of the total power consumption. When the IC technology is below 100 nm, the threshold voltage is decreasing with the decline of the source voltage. The sub-threshold current will increase exponentially due to the threshold voltage reduced, which will make the leakage consumption increased. The proportion of the leakage consumption is increasing in the total energy consumption. It is reported by the ITRS: leakage consumption may dominate in the total power consumption. It is studied that: the energy recovery technology play an important role in reducing the dynamic consumption. Further reducing leakage consumption has an important significance on the basis of the energy recovery circuits.This thesis investigates the SRAM circuit. Dynamic and leakage consumption is optimized. It is mainly studied by the following content.1. It is analyzed the power generation mechanism of the conventional CMOS circuits. The theory and structure of the adiabatic circuits is analyzed in this part. The source of the leakage current and leakage consumption reduction technique is studied.2. The conventional CMOS SRAM circuit is designed. A four-phase adiabatic CPAL(Complementary pass-transistor adiabatic logic) SRAM is designed to reduce the dynamic consumption. The designed CPAL SRAM is optimized by using the leakage consumption reduction technique. The SRAM circuits are simulated with HSPICE. The simulation result verifies the advancement of the energy consumption and the effect of the leakage consumption reduction technique of the designed SRAM.3. A four-phase adiabatic PAL-2N(Pass-transistor adiabatic logic with NMOS pull-down configuration) SRAM is designed, and optimized by the gate-length biasing technique, DTCMOS technique, and power-gating technique. The energy consumption of PAL-2N SRAM reducing about 70% compared with the CMOS SRAM is verified from the layout level with the full-custom design with NCSU PDK 45 nm technology.4. Near-threshold technique is a direct and effective way to reduce power consumption. Through measuring the operation voltage and operation frequency of the SRAM circuit to obtain a minimum EDP(Energy Delay Product), thus the near-threshold voltage is obtained. The simulation results show that: the energy consumption is significantly reduced when the SRAM circuit works in the near-threshold region.