Combination Circuits Design Based On Leakage Power Reduction Technique

With the rapid development of integrated circuits technology, the chip size is increasing, which leads to that the chip power dissipation continues to increase. Low power IC design has become an important research direction. Especially as the process enters deep submicron, the leakage power of CMOS circuits takes a larger part of its total power dissipation. The leakage of CMOS circuits rises exponentially with the feature size decrease, thus the leakage power consumption does not null anymore and can't be paid little attention again. Reducing the leakage power consumption is an urgent problem for low-power chip design.Combinational logic circuits are the basic unit of digital systems, and also the key computing units of microprocessor (MCU) and digital signal processor (DSP). Combination logic circuits are usually on the critical path, therefore they are important factor in the decision of processor performance. Low-power design of combinational logic circuits is significant for power optimization of digital systems.This paper first surveys the mechanism of leakage, and then investigates the leakage power consumption in deep sub-micron process CMOS circuits. We select the combinational logic circuits as the main study object, and research and explore the reduction methods of the sleep and active leakage power consumption for adiabatic logic circuits. On this basis, we can try to propose new forward-looking leakage power reduction techniques for combinational logic circuits, and design low leakage power consumption combination circuits. These proposed combination circuits are expected to provide an alternative implementation scheme for low-power CMOS chips.The main contents of this paper are shown as follows:The six forms of leakage currents and their formation mechanism in deep sub-micron process are introduced in this paper. A variety of leakage current factors are explored. Voltage and temperature impact on leakage current are analyzed. According to the mechanism of leakage currents, this paper summarizes the varieties of proposed leakage power reduction techniques for conventional CMOS and divides these techniques into: process control technology, sleep leakage power consumption techniques and active leakage power consumption techniques.Single-phase adiabatic circuits have been more and more widely used, because their clock trees are easy produced. In this paper, the structure of clock adiabatic logic (CAL) circuits and their working principle are studied, and the advantages of improved CAL (ICAL) circuits are also analyzed. Then single-phase CAL Booth encoding multiplier circuits are presented. Based on the Hspice simulations, the results show its simple structure and low power consumption.For single-phase adiabatic circuits, two adiabatic circuits leakage power consumption reduction technique (power-gating technology and multi-threshold technology) are proposed. Based on this two leakage power reduction techniques, we design ICAL 8-bit full adders respectively, and simulate their leakage and total power consumption in different process. The simulation results show that the two technologies can greatly reduce the leakage power consumption in sleep mode.Base on the fact that leakage power consumption also exist at the working condition, the active leakage power estimation model for single-phase adiabatic are explored and its accuracy is verified. Dual-threshold technology based on ICAL is proposed and low-power ICAL ISCAS c17 circuits are designed. Then p-type logic technology for ICAL logic is researched, and its low power consumption is verified. The low-power p-type ICAL ISCAS 74128 circuits based on dual-threshold technology for active leakage power are presented.