| With the rapid development of IC industry, the size of a device has decreased to the stage of nanoscale; the power density per unit on the chip also becomes larger and larger, so this makes the power consumption rise from speed, area, cost and many other integrated circuit bottlenecks and become the key factor of the SOC chip design. Memory occupies the chip area of more than ninety percent of the system on a chip (SOC). With its good features, Static random access memory (SRAM) occupies the majority of on-chip memory. In recent years, lowering the system power supply to the near-threshold or sub-threshold area can greatly reduce the power consumption of a chip which is also the central idea of the sub-threshold design. All in all, designing a low power SRAM memory cell which can normally work at the near-threshold or sub-threshold area is of great significance to reduce the power consumption of the SOC.Based on the research status of low power SRAM at home and abroad in recent years, this paper starts with reducing the power consumption of basic cells in SRAM storage array and focuses on resolving the urgent demand for low power consumption of SOC nowadays. After detailed introduction and analysis of several mature basic memory cells including the traditional six-transistor cell in the development process of SRAM, this paper proposes a low power nine-transistor memory cell which works in the sub-threshold region. The power consumption of SRAM can be divided into static and dynamic power consumption; SRAM memory cells which works in the sub-threshold area have a very low power consumption but their stability is also more susceptible to process, supply voltage and temperature (FVT). In the last part, the paper makes a simulation and verification of the nine-transistor memory cell in the aspects of stability, reading and writing speed, power consumption. Compared with the traditional six-transistor memory cell, the design in this paper does have excellent characteristics. |
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