Dynamic threshold technique for soft error mitigation in nanometer CMOS circuits

The chip power dissipation and soft error reliability are two important challenges against chip designers as technology advances. A number of techniques have been proposed to decrease power dissipation in Integrated Circuits (ICs). As designers try to address power dissipation issues, its impact on soft error robustness should be considered. This is important as it will help us choose designs which are both power efficient and radiation soft error tolerant.;This work first analyzes the effects of threshold voltage on soft errors and soft delay errors in combinational logic circuits. The analysis results show that higher threshold voltage (which is generally used for reducing power dissipation in ICs) increases soft error susceptibility of the combinational logic circuits. On the other hand, the lower threshold voltage increases the circuit robustness to soft errors and soft delay effects. In this work, various dynamic threshold (DTMOS) based schemes have been examined for their soft error and soft delay tolerance as the DTMOS techniques are considered as a promising candidate for low-power and high-speed circuit devices.;Among DTMOS techniques considered, the standard DTMOS technique shows the best characteristics in terms of Soft Error robustness because of increased current drive. It has also been found that the standard DTMOS technique can be successfully combined with driver sizing approach in mitigating the Single Event Transient and Soft Delay Effects. This combined approach results in considerable chip area savings compared to driver sizing alone. This is possible since standard DTMOS gate is more robust to radiation transients compared to a conventional one because of increased critical charge.