Low Power Consumption And Low Frequency RFID Study On The Baseband Processor

This thesis discusses the operational principles of the baseband-processor for the low frequency (LF) RFID tag. Besides, the thesis also closely analyzes the implementations of the low power designs on this baseband-processor.Firstly, the importance of low power design of RFID system is introduced, the protocols that LF tag should be compatible with are presented in detail and the operational principle of a novel low power circuits - adiabatic circuits is introduced. The power consumption of adiabatic circuits is detailed analyzed and the comparison of different kinds of such circuits has been made, according to their operational principles, characteristics and power consumption.Secondly, a novel low power LF baseband-prcessor is designed in this thesis. An asynchronous data decoding technique is proposed to solve the clock halting problem during 100% ASK modulation mode; a new command decoder is designed to increase command decoding speed of the LF system; an anti-interference method is applied to enhance the interference immunity of the LF tag; the pipeline structure is implemented in the working of baseband-processor which increase the working speed of LF tag. Other techniques like power management and architecture optimizations have also been incorporated into the design to reduce chip power consumption. The final design is fabricated using a SMIC0.18μm CMOS standard process and the experimental results show the circuit can well satisfy its design requirement.Thirdly, several issues in the implementation of adiabatic circuits to LF baseband-processor are discussed: the compatibility with traditional CMOS circuits, the assignment of the combinational logic and the sequential logic for adiabatic circuit and the number of fan-in and input stages. For the first issue, a novel quasi - static adiabatic logic family is implemented. For the second and the third issues, a new method to replace the traditional CMOS circuits with the adiabatic ones is proposed. The function of the adiabatic LF baseband-processor is verified. The design is fabricated using a SMIC0.18μm CMOS standard process.