| While in the family of the semiconductor memory, the Static Random Access Memory (SRAM) is definitely the workhorse for on-chip data storage owing to its robust operation, high speed, and low power consumption relative to other options. Also SRAM is fully compatible with standard COMS process. As SRAM is accounting for the large share of area in microprocessor and SOC, and is vulnerable to single event upset (SEU) in the radiation environment, immediately needs a solution for reducing the power and improve the reliability of SRAM.Low voltage design is the most effective way to achieve low power consumption, because it can significantly reduce both dynamic power and static power. The design is an ultra-low-power SRAM with the supply voltage below the transistors threshold voltage. Sub-threshold circuits have many applications, even spacecraft electronics may benefit. To mitigate SEU, a Dual Interlocked storage Cell (DICE) based SRAM cell was used. This structure also can improve cell’s SNM at sub-threshold operation.The64×8bit SRAM was designed and simulated in SMIC180nm CMOS process. Simulation results suggest that it can operate at sub-threshold voltage and is radiation hardened. The SRAM cell can still operate at150mV. The SRAM’s operating frequency at VDD=0.3V is up to180KHz with power dissipation208nW, while it is9.62MHz at VDD=0.5V dissipating13.98nW. By simulation, the circuits are demonstrated to be rational under sub-threshold voltage, and do have the feature of ultra-low-power and radiation hardened. |
