Leakage Power Reduction Technique In Adiabatic Circuits

The technology feature size of modern mainstream integrated circuit has entered thenanometer era. The number of transistors on a SoC chip system have generally been more thanthousands gate level, and the chip work clock has reached more than GHz, thus the energyconsumption of the chip increases sharply for the number of transistors increasing and theoperating speed enhancing. However, oversize energy dissipation may lead to a decline in the chipperformance, influence on the stability of chip and produce a series of problems includingcomplicated encapsulation heat dissipation. Therefore, the energy dissipation of integrated circuitchip seriously restriction the number of transistors and further improved of the chip performance.Along with sizes of MOS transistors further scaling down, the leakage dissipation caused byleakage current gradually increase which had been relatively smaller, when the process arrived at65nm or below, leakage dissipation become the main source of circuit energy dissipation insteadof dynamic energy dissipation. Researches show that energy recovery logic circuit has madesignificant effection in saving dynamic energy dissipation, consequently the leakage dissipationcaused by leakage current in the energy recovery logic circuit will be far serious than the sameissue in the traditional CMOS circuit. How to reduce the leakage energy dissipation in energyrecovery logic circuit becomes a difficulty in low-power design.In this paper, on the basis of analyzing the source of leakage current in CMOS circuits,combinational logic circuit and sequential logical circuit are seen as the research object, and how toreduce the leakage energy dissipation technical in energy recovery logic circuit has been discussed.This paper are mainly divided into the following several parts:1. Introduce the generation mechanism of energy dissipation in CMOS circuit, then analysisthe main source of leakage current in CMOS circuit and the corresponding optimization methodfor leakage dissipation.2. Introduce the operating principle of PAL₂N （Pass-transistor Adiabatic Logic with NMOSPull-up Configuration） energy recovery logic circuit, and put forward the corresponding estimatingmethod for leakage energy. Towards the sub-threshold leakage current, the PAL₂N logical unitwhich operated together by gate-length biasing and dual threshold CMOS has been designed. Howto reduce the gate electrode leakage current has been further studied on the basis of optimizing thesub-threshold leakage current, and the PAL₂P logical unit which operated together by p-typeCMOS circuits, gate-length biasing and dual threshold CMOS has also been designed. The simulation results of layout design show that the proposed scheme has achieved a better result onoptimizing the leakage dissipation.3. Analysis the operating principle of CPAL （Complementary Pass-transistor Adiabatic Logic）energy recovery logic circuit, and put forward the corresponding estimating method for leakageenergy. The CPAL logical unit which operated together by p-type CMOS circuits, gate-lengthbiasing and dual threshold CMOS has also been designed. The CPAL flip-flop functioned togetherby gate-length biasing and dual threshold CMOS, as we dissipation as the CPAL flip-flopfunctioned with the addition of p-type CMOS circuits, have been designed. The simulation resultsby HSPICE show that the proposed scheme can effectively decrease the total dissipation andleakage dissipation.4. A new improved single-phase ECRL （Effective Charge Recovery Logic） logic circuit hasbeen proposed with studying the structure of ECRL logic circuit, and the corresponding modifiedflip-flop has been designed. The sequential benchmark circuit has been designed using the leakagedissipation technology based on improved ECRL logic, results show that the proposed scheme hassimple structure and possess the characteristic of low leakage dissipation.