The Design Of Single-rail MOS Current Mode Logic Standard Cells

With the popular portable devices in recent years, the power dissipation and speed of chips are put more attention. Therefore, high-speed and low-power system design becomes the focus of the integrated circuits design. And one way of high-speed and low-power circuit design is to optimize the circuit structure. The low power dissipation is the advantage of MOS Current Mode Logic(MCML) circuits in high-speed systems, and the MCML circuits are widespread concern. MCML circuit has two structures: dual-rail MCML(DRMCML) and signal-rail MCML(SRMCML). They have the advantage of strong anti-interference ability and wide frequency range, and the power dissipation doesn’t change with frequency. Compared with DRMCML, SRMCML have smaller area and relatively simple connecting lines to achieve the same logic function with MOS transistors.The design flow based on standard cells library have the absolute advantage in digital integrated circuits design. The performance of standard cells directly affects the system design. The standard cells data plays a leading role in the digital design flows, and it is significant to develop a high performance standard cells library. The development of SRMCML standard cells is the most direct method to obtain the high-speed and low power dissipation system in a same process node. This method shored the product-to-market time. The DRMCML standard cells cannot be characterized and synthesized because of their differential inputs features, so the design of MCML standard cells library can only use the signal-rail MCML(SRMCML).Firstly, this thesis introduces the SRMCML standard cells library building method and flow. Secondly, the significance of SRMCML standard cells library in the high-speed and low-power system is discussed. Then, the SRMCML standard cells library design technology is introduced in detail, and design a SRMCML standard cells package in SMIC 130 nm process to support for the ASIC design.According to the standard cells library design flows, the thesis can be divided into several sections as follows:1. The technology files of SMIC 130 nm process are analyzed. We design and optimize SRMCML circuits to achieve the performance optimization;2. The layouts of circuits are drawn. The layouts must be meet the process layout rules, for instance standard cell height, the minimum cell width, the power metal width, and the routing pitch rules and so on. The PIN must be located in the pitch of the cross point, and the standard cell width must be integer times of the metal2 pitch;3. The physical library is designed. We get the physical library for placing and routing by Cadence Abstract. The library mainly contains metal layer location and PIN and so on.4. The timing library is designed. We use Calibre to extract parasitic parameter, then invoking Liberty NCX and Hspice to extract the NLDM(Nonlinear Delay Model) timing library.Finally, we design an unsigned 16-bit multiplier from RTL to GDSII to verify the performance correctness of the standard cells package. The results show that SRMCML standard cells package is correc and can achieve the expected goal.