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Exploitation And Assessment Of A Small Standard Cell Library Based-on FinFET Structure

Posted on:2020-02-12Degree:MasterType:Thesis
Country:ChinaCandidate:G ZhuFull Text:PDF
GTID:2428330602952301Subject:Engineering
Abstract/Summary:PDF Full Text Request
With the decreasing of integrated circuits of critical dimension,exploiting standard cell library by adopting the CMOS structure is difficult to meet the design of large scale and high complexity.Due to the FinFET structure can control the circuit on and off at both side,effectively reduces the leakage current,is a good choice to exploit standard cell library.As a bridge between digital front-end and back-end physical implementation,the performance of standard cell library largely determines the final performance of chip.As a reusable and reliable basic IP library,its performance determines the chip parameters.This paper uses FinFET three-dimensional structure to design a set of small standard cell library,using the relevant EDA tools to introduce the design process in detail,describes the relevant design optimization strategy.And designed a test code,the application of the mainstream ASIC design process,through the general direction and low power clock gating direction and the application of higher node standard cell library for comprehensive and physical implementation,the standard cell library performance of the horizontal and vertical comparative analysis,highlighting the basic unit library performance advantages of the design in this paper.Focus on test code design verification and library performance evaluation.VCS tool are used for functional and post-simulation in test code design;Using Design Complier tool to test the code application high node and Design the basic unit library routine comprehensive,integrated with low power consumption direction to assess their performance report;With formal verification tool Formality of four netlist after comprehensive function conformance verification and layout;The Static Timing Analysis tool PrimeTime is used to analyze and verify the timing and signal integrity after physical design.Using the placing and routing tool IC Compiler to complete physical design for four netlists,and then analysis the performance advantage for new technology node standard cell library.Finally,the author makes a comparative analysis of the relevant data,which proves the excellent performance of the small standard cell library designed in this paper and achieves the design goal satisfactorily.
Keywords/Search Tags:Standard Cell Library, FinFET, Performance, Power, Area
PDF Full Text Request
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