Standard Cell Library For Low-power Technology

VLSI design spent great revolution in the past 20 years.Power dissipation has now become the number one challenge facing today's chip designers.45nm products of the leadership semiconductor company are under mass production.High power dissipation is brought up with transistor size scaling down though which also induce smaller chip are and quicker frequency.The most typical is leakage power.Leakage power con little in total power dissipation before 180nm technology.But unfortunately leakage power increases rapidly with the threshold voltage decreasing.Even more leakage power is equal to dynamic power in 65nm technology.Low power will become main stream in IC design but high speed design.This paper aims at study a special library for low power design flow.Firstly,this paper looks back the concept and category of power,explains the main idea of decreasing power and discuss the popular low power technology.Since standard cell library plays an important role in low power flow.Secondly, this paper discusses the influence of designing a standard cell library and the complete design flow.Such as Power Gating / Isolation / Level Shift / Retention Flip Flop / Clock Gating are main cells in low power library.Hence we focus on the circuit design of these cells and verify the timing and function with HPSICE especial on Level Shift / Retention Flip Flop / Clock Gating.