The Study And Optimization Of 0.18μm CMOS High-speed Standard-cell Library

The notable preponderance of cell-based design to full custom design is that cells are designed and verified only once for given technics, then can be reused many times, so the cost of design is proportioned. Cell-based design is more and more popular for shortening time-to-market and automatizing the design. Standard-cell library offers good supports for every phases of cell-based design flow. Its quality is very important to the quality of the design of a chip. So it plays a very important role in cell-based design.We are designing 0.18μm high-performance X DSP ourselves now. The application requests high-performance of the DSP, but the business standard-cell library of foundry can't satisfy request like that. For reason above we design 0.18μm standard-cell library ourselves, and optimize its performance continually. After taking part in building the library, my major work includes that optimizing the buffer library following the methodology of building the library and some cells' delay at cell design level. The work of this paper is showed as follows.1. We built the buffer library following the superior buffer algorithm and K_Center algorithm. At first, we bring forward the timing model of inverter chain to optimize the superior buffer algorithm. Then these two algorithms were programmed with Matlab. According to results of programs we designed the buffer library's layout, we also extracted the file including technics and timing information from the layout. The performance analysis of new buffer library indicates that it can bring some improvement of the synthesis result and better result of buffer insertion. We can also change the value of D which is called threshold value to increase the size of buffer library for improving the library's performance.2. Optimizing the clocked cell. This paper describes that how to optimize structure and sizes of clocked cell for improving the frequency of the chip based on synthesis result after the library was first built. It designed the layout and gave *.db and *.lef files. The result of layout simulation indicates that the function of cells redesigned is correct, reliability has no reduce, area doesn't add, the delay of each cell has the decrease of more than 12%, the most decrease is 21.9%, the slowest cell delay has a decrease of 245ps, the power descends a little.