An Improved Standard I/O Cell Library And ESD Design Based On 40nm Process Technology

In this thesis, the research mainly forcused on discussing on a process of 40 nm standard CMOS I/O Library design from two specific, that is I/O interface circuit and ESD chip architecture. The project comes from SMIC of a customer's product,what I participated is update the Library, including the entire standard I/O library design optimization, pre-simulation, post- simulation after layout and setting Testchip item.In aspect of I/O, it is mainly discussed composition, basic structure of the circuit,working principle and individual module structure. What I participated in is optimizing such parameters as slewr/slewf, delayr/delayf, duty cycle in I/O transmitter mode. In condition of 5 MHz and TT corner,slewr/slewf is optimized from the original parameter around 92% to 95%~100%, delayr/delayf is optimized from the original more than 105% to 95%~100% and duty cycle is optimized from the original 53% to about 50% optimization.Due to changes in the circuit structure, it is needed to updated such parameter values as IOH, IOL, VT, VT+, VT- at different VDD, VDD25 voltages and different process corner(TT, FF, SS). The differences between the value of the old I/O library version and the new is small, only a slight change occurred. There are nine combinations of VDD, VDD25 voltage that is(0.99 v, 1.62v),(1.1v, 1.8v),(1.21 v, 1.98v),(0.99 v, 2.25v),(1.1v, 2.5v),(1.21 v, 2.75v),(0.99 v, 2.97v),(1.1v, 3.3v),(1.21 v, 3.63v). Adding SA, SB parameters in pre-simulation to pre-assess the impact brought by various types of layout parasitics and increase the accuracy.In terms of ESD, Power cell and I/O structure are involved to ESD-related content. The thesis focuses on the basic principles of ESD, ESD model, several test structures, the TLP curve and ESD protection network. I participated in optimizing Power Clamp structures.Firstly, modify the p MOS feedback with three inverters Power Clamp structure to the conventional feedback-free with one inverter Power Clamp structure. The conventional structure not only solves the problem that HBM model does not fully discharge in old version of the library because the feedback time error, but also shortens the propagation delay time. In addition, the simple structure decreases the Power Clamp leakage in normal work condition. Secondly, enlarge the large ESD n MOS sizes. This method increases the discharge current in ESD period and at the same time it is equivalent to reducing the ESD discharge time.The simulation result of updated 40 nm standard I/O library shows that the pulse signal from core to I/O is optimized. Furthermore, new structure of Power Clamp optimizes discharge function of ESD, discharges 2KV HBM efficiently and reduces the leakage current.