Design Of 40nm Standard Cell Library For 0.6V Low Voltage

Reducing voltage has been the effective way to improve energy efficiency of the CMOS circuits. Studies have shown that circuits' highest energy efficiency points are in the area of near threshold in today's advanced technology. But compared with the nominal working voltage, the performance of near-threshold standard cell deteriorates 10 times, limiting the performance of the system. Thus, this thesis studies the design of near-threshold high performance standard cell.The performance of the near-threshold standard cell almost depends on size and layout equally. Based on this characteristic, this thesis performs joint optimization of multiple parameter on the near threshold standard cell which have three characteristic. Firstly, seven key design parameters that affect performance including widths, fingers and so on and five feasibility programs including sizing, convex well structure and so on are identified to ensure optimal standard cell design. Secondly, the mathematical optimization model of the design of near-threshold standard cell is established, including design variables, delay model, area model and objective function. The influence of the layout on the delay and area is quantified in this model which thus realizes the joint optimization of parameter design and layout design. Thirdly, for design goals with different trade-off between delay and area, the design of standard cells is completed. What's more, the timing accuracy of near-threshold standard cell library is studied. A method is proposed that segment the stimulus waveform and identify segmentation coefficients based on extensive test circuit. With this method the timing accuracy of the libraries increases to 6.8%.The design of standard cell library for near threshold is completed and validated based on SMIC 40nm. The metrics including delay, energy, energy delay product and area are validated. The validation are based on the synthesis and analysis of ISCAS85 with compared with foundry original library. The results show that compared with the foundry original library, the average improvement of the performance of the circuit synthesized with the D7A is 16.47%.The average reduction of energy is 30.38%.The average gain of energy delay product is 41.86%.The average area cost 15.8%.