The Design Of Standard Cell Library Based On The SMIC0.18um EEPROM Process

With the rapid development of integrated circuit technology, the semiconductor processhas been into the nanometer level from the deep sub-micron level, transistor-leveldesign is becoming increasingly complex and the chip scale of SOC has entered theGLSI era from the first LSI. In today’s increasingly competitive market, in order to meetthe market demand, speed up the development pace of the chip, shorten the chipdevelopment cycle and reduce the cost of chip R&D, ASIC design method based onstandard cell libraries came into being.The ASIC design must get a content-rich fully functional standard cell library supportfrom the description of the behavior of the system-level, logic synthesis to automaticplacement and routing, timing verification and back-end gate-level simulation. Thispaper makes systematical research and practical work and eventually established acomplete set of low-voltage low-power standard cell library with basic properties tomeet the design requirements based on the SMIC0.18um EEPROM deep submicronprocess, which consists of the technology file, map file, synthesis library, simulationmodel library, HSPICE netlist for LVS, Milkway library, antenna fule file and thedatasheet about the library, and passes the verification of EDA tools, including designcompiler, astro from synopsys and NC-Verilog form cadence.