Creating Library Technology Of 0.35um Standard Cell Library And Implement

The development of Microelectronic technology has gone through LSI , VLSI, ULSI ages and come into GSL age in 1995. As the representative of hi-technology, Integrate Circuit technology holds the balance of power in the development of world economy. ASIC develops faster due to the short development cycle, low development cost and high reliability. Good functional cell library is a bridge to link ASIC users and process line. It is impossible to have high level ASIC design without good cell library. In this case, big cell library has become a barrier for shortening the time to enter to the market of VLSI products.In recent years, design based standard cell is the main stream design style. Standard cell library is getting bigger and bigger, some have been over 500 units. However, to create, verify and maintain these standard cell libraries need a great lot of time, manpower and material resources. Moreover, errors often occur in the cell design and cell characteristic process. At present, the technology is diversified and changes quickly. So a cell library needs to be maintained constantly.This paper mainly tells about the creation library flow and varieties of 0.35um standard cell library, including symbol library ,P&R library ,synthesis library ,simulation library ,timing library ,layout library . In these cell libraries, there are 420 cells.cells can be grouped into the following four categories: basic cells , I/O cells, analog macro elements and macro elements, including SRAM ,ROM with all kinds of scales ) . Candece and Synopsys are used in creating library .The emphasis is improving creating library technology in layout library , such as optimizing cell withs and optimizing cell heights ,furthermore, optimizing routing .To do this minimize chip size .