Design Of Novel Trench LDMOS And N Covered SJ LDMOS

With the development of power integrated circuit(PIC), lateral double-diffused MOS(LDMOS) is widely used in power integrated circuit because of its small switch power dissipation, good frequency characteristic, compatibility with CMOS technology and other excellent features. While the silicon limit relationship between the breakdown voltage and the specific on resistance limits its development. The method to design a LDMOS device with high breakdown voltage and low specific on resistance attracts the attention of researchers. At the same time, the emergence of super junction has broken the silicon limit relationship of traditional power devices, but when it is applied to lateral power devices, the breakdown voltage becomes lower because of the substrate assisted depletion effect. Therefore, the way to eliminate substrate assisted depletion effect in lateral super junction devices and improve the breakdown voltage of the device also attracts the attention of researchers.In this paper, the main work includes three aspects below:Firstly, a novel silicon LDMOS structure with low dielectric coefficient trench(LDT-LDMOS) is proposed in this paper. In this structure, the breakdown voltage can be increased, because the drift region is folded by the low dielectric coefficient trench which can increase the effective length of the drift region. According to the RESURF theorem, the doping concentration of the drift region is increased for the reason that the drift region area is occupied by the low dielectric coefficient trench, it is clear that the specific on resistance of the device can be reduced by the high doping concentration. In this paper, air and Si O2 are chosen as examples for the low dielectric coefficient material filled in the trench. The results of the ISE-TCAD software suggest that, when the drift region is in a scale of 3.5 micro meter, the specific on resistance of 2.47 m?·cm2 and 2.58 m?·cm2obtained from LDT-LDMOS by the introduction of air and Si O2 are decreased by about 28.2% and 25% compared with that of conventional LDMOS which is 3.44 m?·cm2, the breakdown voltage of 149.4V and 134.4V obtained from LDT-LDMOS are increased by about 78.9% and 61% compared with that of conventional LDMOS which is 83.5V. What is more, the unit voltage of 30V/?m known as silicon limit in the conventional structure is exceeded by that of LDT-LDMOS which is about 42.7V/?m and 38.4V/?m, respectively.Thus under the same breakdown voltage, LDT-LDMOS can be used to reduce the surface area of device and improve the device integration.Secondly, a novel SJ-LDMOS structure with a N type covered layer(N covered SJ LDMOS) is proposed in this paper. The N covered layer is formed by ion implantation or diffusion on the surface of P pillar in the super junction region. The substrate assisted depletion effect of lateral super junction devices is eliminated by the interaction between the N covered layer and the P type substrate, which balances the charges in P pillar region and N pillar region, and improves the breakdown voltage of the device. At the same time, when the device is on, the specific on resistance is reduced due to the extra conductive channel provided by the N type covered layer. The results of the ISE-TCAD software suggest that, when the drift region is in a scale of 5 micro meter, the breakdown voltage is 119 V, and the specific on resistance is 1.58 m?·cm2. The breakdown voltage of a traditional LDMOS and a traditional super junction LDMOS is 103 V and 55 V, respectively. Thus when compared with these two devices, the breakdown voltage of N Covered SJ-LDMOS is increased by 15.5% and 116.3%, respectively. For the specific on resistance, the traditional LDMOS and the traditional super junction LDMOS is 2.6 m?·cm2 and 1.9 m?·cm2, respectively, which is reduced by 39.2% and 16.8%, respectively.Finally, in view of the differences between the two novel structures above and traditional structures, two additional processes adaptive to the two novel structures are put forward on the basis of traditional devices. The etching and deposition processes are added to form the low dielectric coefficient trench. The ion implantation process on the surface of P pillar is added to form the N covered layer. The concrete processes of the two novel structures are given.