Research On 8-channel Pipeline ADC

With the rapid development of wireless communication technology and integrated circuits, ADC with high-speed and high-precision is always a major building block of modern communication system. Currently, the best compromise of ADC between high-speed and high-precision is pipeline ADC. After a long study, performance of the structure in a single-channel Pipeline ADC has reached the limit under specific conditions, especially in the conversion rate.In this context, multi-channel Pipeline ADC breaks through the bottleneck of single channel Pipeline ADC in the sampling rate. However, mismatch among the channels affects the accuracy of the multi-channel Pipeline ADC. These mismatches conclude offset, gain, bandwidth, the reference voltage, the sampling time and so on.Currently, with the improvement of the operating speed of the electronic device, the application in which the conversion rate of the ADC is also necessary to increase. There are two methods which can increase the sampling rate, the one is to improve the process, and the other one is to use multi-channel ADC in parallel to achieve higher sampling rate. Due to the current process has been more advanced, so generally the second method is adopted. When analog input signal need to be processed, input signal can choose channel through a multiplexer, and the selected channel process the input signal at the moment, and multi-channel analog input signal is sampled alternately, so the sampling rate could be increased. Therefore, an 8-channel Pipeline ADC whose sub-channel ADC with14-bit accuracy and 12.5 MHz sampling rate was designed. In 0.5μm CSMC CMOS process conditions, according to the consider compromise among gain, bandwidth, power consumption and noise, the sub-channel ADC is determined by 12 stages of 1.5-bit and a 2-bit Flash ADC composition. Among them, the two-phase non-overlapping clocks control the odd and even stage work alternately, all stages after delay alignment and redundancy calibration ultimately by the dual-port output 14-bit digital signal.In the sub-channel Pipeline ADC of 8-channel Pipeline ADC, critical circuit modules include margin gain circuit, operational transconductance amplifier, dynamic comparators, common mode feedback circuit and delay calibration circuit. In the system level circuit design, the key chip-level modules contain reference voltage generation circuit, bandgap reference generator circuit, bias current generator circuit, clock control circuit, reset circuit and clock tree.These modules and the entire system are simulated, the basic requirements is achieved in this design. In 0.5μm CSMC CMOS process, three layers of metal and two layers of polysilicon were taped to achieve an 8-channel Pipeline ADC. The system of 8-channel Pipeline ADC was simulated by Spectre in Cadence software. When the frequency of input signal is 6.25 MHz, the simulation results revealed that the DNL achieves +0.65/-0.80 LSB, the INL achieves +0.78/-1.58 LSB, the ENOB achieves 12.06 bits, the SFDR achieves 80.96 dB and the SNR achieves 74.3612 dB. Its performances reached the original design goal.