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Design Of A High-Performance Pipelined A/D Converter Integrated Circuit

Posted on:2007-02-05Degree:MasterType:Thesis
Country:ChinaCandidate:X ChenFull Text:PDF
GTID:2178360182986870Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
In mixed signal systems, Analog-to-Digital Converter (ADC) is a crucial portion. The rapid development of DSP techniques in application areas such as video signal processing and wireless communication keep demanding high performance of monolithic ADC. The Pipelined ADC architecture has the characteristics of high sampling rate as well as high resolution. Generally, the Pipelined architecture is most appropriate design plan for ADC systems beyond 10bit and 1MSamples/s.Proposed in this thesis, base on 0.6μm CMOS technology, a 10-bit high performance low power pipelined analog-to-digital converter is designed and implemented. A sample-and-hold amplifier (SHA) was used to improve the signal-to-noise and distortion ratio (SNDR) performance and the linearity of ADC. Sampling capacitors scaling technique was employed to reduce the power dissipation. Using digital correction technique relaxed the offset requirement of the comparators to 0.25V, so the low power dynamic comparator was chosen. The simulation and experiment results reveal that the ADC designed with this method achieves the SNDR of 58dB or the ENOB of 9.34 at full speed of 20MHz when input frequency is 3MHz. Furthermore, the ADC consumes only 49mW power at 5V supply voltage with a low power operational transconductance amplifier (OTA) and the dynamic comparators. The design work attained the specifications of high performance ADC system which is applicable for wireless communication and video signal processing.In the whole thesis, first, the fundamental theories of pipelined ADC were analyzed, and the non-idealities, major error sources and main design constraints were discussed. After that, the design considerations and optimization of the most important circuit structures, including Switches-Capacitors, OTA and Dynamic Comparator were discussed at the third and forth chapters. Moreover, the consideration of feasibility and reliability in back-end design was analyzed at the fifth chapter, while the overall simulation and experimental results were summarized.
Keywords/Search Tags:Pipelined ADC, S/H Circuit, Op-amp, Dynamic Comparator, Digital Correction
PDF Full Text Request
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