Design And Research Of The Gate ESD Protection For RF LDMOS

As the fast development and popularity of cellular wireless base stations and the third generation wireless communication system, higher and higher demands are proposed for high frequency amplifier. and it is also a good opportunity for its development. RF LDMOS with its low cost, high efficiency, high linearity and high integration, have been gradually occupied the market, and more and more attention has been paied on the research on RF LDMOS. Unfortunatly, the research is very lacking in our country, so that, most of the high-performance RF LDMOS need to import, so it is significative to do more research on RF LDMOS.With the continuous development of semiconductor technology, the size of devices is shrinking, RF LDMOS also cannot be exception. At the same time, the influence of ESD pluse is stronger, especially the breakdown of gate oxide. The RF LDMOS cannot protect itself anymore, designing effective RF ESD protection is necessary and inevitable. This paper is to design the gate ESD protection for a RF LDMOS, its working frequency is between 2.7GHz and 3.1GHz, the thickness of its gate oxide is 30 nm, so the gate breakdown voltage is about 30 V. The ESD ability of the designed protection devices should be above 2KV, and the performance of RF LDMOS cannot be affected.The sensitive to the effects of parasitic parameters makes the RF ESD design much more complex. At first, this article will introduce the generation and protection design methods of ESD basing on the theory of tradition ESD design. Then, the difficulty of RF ESD design is analysised to know the problems need to be solved.In this paper all the commonly used ESD protection devices are simulated by Silvaco to understand the characteristics, under the condition of RF LDMOS’s manufacturing process. At the meantime, some methods to improve the ability are used to meet the design requirements, such as changing the doping concentration and the distance between the electrodes. Then some application methods to reduce the parasitic capacitance are introduced by forming a series of parasitic capacitances. The LC resonance circuit is also used in this article. At resonant point, the impedance of the LC circuit can be infinite or zero, which can be used to isolation or elimination the parasitic capacitance of the RF ESD devices.The first batch of devices has been verified, inculd polydiode, stacked NMOS and NPN with poly gate. The test result shows the polydiode and NMOS almost can meet the design requirements, but the NPN’s triggering voltage is too high. Although the result is not satisfying, it can also help the design later.Finally, some of the layout optimization techniques which can make the device better were listed.