Study On The Electro-thermal Effects Of LDMOS Power Devices

LDMOS (Lateral Double-diffused MOS transistors) power devices are widely used as output drivers in switching modes in SPIC (Smart Power Integrated Circuits) because of their low cost and specific performances. It is significant that the reliabilities of LDMOS devices play a more and more important role responsible for the reliabilities and life-span of both themselves and SPIC with the development of micro-electronics technology. LDMOS devices often operate under DC (Direct Current) or AC (Alternating Current) conditions, where AC includes continuous multi-pulses and the ultra transient single pulse such as ESD (Electro Static Discharge) and EOS (Electro Over Stress). When LDMOS devices operate in switching modes under continuous pulses of applied electric power, the self-heating effects induced by power dissipation occurs and the temperature will fluctuate within the devices. When LDMOS devices operate in self-protecting modes under the ultra transient single pulse such as ESD protection, the ultra transient high current passes through gate-grounded or gate-coupled LDMOS devices and the thermal runaway will often happen. However, LDMOS devices often show a very small thermal safe operation area and striking ESD/EOS vulnerability. If the maximum temperature of LDMOS is beyond the rated range, LDMOS devices will fail and thermally break down, and wires will burn away in SPIC, and other transistors and circuits nearby will degrade, and even chips will melt. It will be especially useful to understand the responsible mechanisms in order to optimize the thermal safe operation area. Therefore, the lattice temperature of LDMOS devices is an important issue.In this thesis, the basic responsible physical mechanisms of electro-thermal effects and temperature characteristics mentioned-above have been explored and analyzed for 40V-LDMOS power devices. Then the main results are investigated and veritified which correspond to both switching mode during continuous applied pulses and ultra high voltage/current stress during a single unexpected transient pulse such as ESD conditions. The results given here can be used as a criterion for design the thermal safe operation condition of power devices. The author's original main work is summarized as follows, especially in Chapter 3, Chapter 4, Chapter 5 and Chapter 6.Firstly, the specific temperature formulas are given and verified to describe periodical characteristics of lattice temperature of LDMOS devices during both continuous multi-pulses and a single pulse of applied electric power with equal thermal circuits, and the rise and fall processes of temperature during a single pulse is described in detail. There are many parameters responsible for the lattice temperature of LDMOS devices such as the initialization, thermal characteristics including thermal resistance and thermal capacitance, the details of applied pulses. Under continuous pulses LDMOS devices will have the periodical rise and fall processes of temperature, then transient response and steady response of lattice temperature are proposed and analysied.Secondly, the relation between the maximum temperature and the switching conditions of LDMOS devices under different frequencies is studied. The results show that the maximum temperature in the device depends on the thermal capacitance, the power dissipation, the duty circle and the time of continuous operating under a high switching frequency. Whereas under a low switching frequency, the maximum temperature not only depends on those four parameters, but also depends on the thermal resistance and the period of the cycle.Thirdly, the electro-thermal effects of GG-LDMOS (Gate-Grounded LDMOS) under ESD stress are studied. Under ESD stress the intrinsic bipolar transistor will operate. The different output characteristics of GG-LDMOS's intrinsic bipolar transistors by the isothermal and non-isothermal methods are compared and analyzed. The space distribution characteristics of GG-LDMOS are described and the influence of delay time of lattice temperature on delay time of drain voltage is proposed. It is shown that the results of the non-isothermal method are more consistent with experimental data than those of the isothermal method. With the non-isothermal method, the better output characteristics of GG-LDMOS can be gained, and the location where thermal failure will occur can be estimated.Fourthly, the electro-thermal effects of GC-LDMOS (Gate-Coupled LDMOS) under ESD stress are studied. The influence of gate voltages on temperature of GC-LDMOS under ultra-high transient currents is studied. In comparison with gate-grounded conditions, the temperature in the device rises when gate voltages are positive which add the injection efficiency of electrons in intrinsic bipolar transistor, and that the temperature falls when gate voltages are negative which reduce the injection efficiency of electrons in intrinsic bipolar transistor. The distributions of electric fields, conduction currents and dissipated power densities under different gate voltages are investigated and compared. It is proved that positive gate voltages weaken the ESD capability of GC-LDMOS, and that negative gate voltages enhance the ESD capability.