Research On Low-capacitance ESD Protection Devies

As the rapid development of semiconductor process technology and integrated circuits, ESD(Electrostatic Discharge) has been increasingly influencing on the reliability of IC products. ESD protection confronts with more and more difficulty and challenges. Especially in the field of ESD protection of ICs under high frequency, the parasitic capacitance of high robust ESD protection devices will have a great influence on the circuits. In this paper, the research and optimization of ESD protection devices are presented.The operating principle and capacitance characteristics of the common ESD protection devices such as diode, MOSFT and SCR are researched. The forward diode has a strong ESD protection capability and small parasitic capacitance; MOSFET is not suitable for ESD protection under high frequency, because a lot of parasitic capacitance is brought in by the gate structure; SCR can achieve strong ESD protection capability in a small chip area, so it has small parasitic capacitance. But it also has high trigger voltage and low holding voltage.The influence of size on parasitic capacitance of N+/Psub diode is presented. And a method is proposed to reduce parasitic capacitance by optimizing the layout structure to increase the perimeter area ratio of p-n junction. Waffle and octagon layout and the corresponding diode layout of removing the central N+ implant region are designed.Low parasitic capacitance characteristics of layout with hollow is much better than layout without hollow. Besides, the parasitic capacitance characteristic of octagon diode is superior to waffle diode.In order to lower the triggering voltage of conventional SCR, efforts have been made to optimize the layout of SCR and MSCR. SCR and MSCR with waffle layout implementation are designed to reduce parasitic capacitance without degradation of ESD protection capability. Besides, reducing the trigger area of MSCR can effectively reduce the parasitic capacitance with the trigger voltage constant. DDSCR can reduce parasitic capacitance by connecting two internal parasitic capacitances in series.Increasing the distance of N-well and N+ area in P-well can raise the holding voltage at the cost of parasitic capacitance increase.