Research On Low-capacitance ESD Protection Devices Based On Several Processes

Electrostatics discharge event is a normal phenomenon which caused the failure of integrated circuit(IC).As the critical dimension goes small and the frequency of the IC goes high,the area of the chip is smaller and smaller;the requirement of low capacitance for the ESD device becomes stricter.For the RF circuit,the robust and low capacitance of the ESD protection device are researched.And the structures,principles and parasitic capacitance are discussed and experimental in 0.18 ?m CMOS process,0.35?m SiGe process and 55 nm RF CMOS process.The works of this thesis are shown below:Firstly,three ESD physical test models and two special test assessment models are introduced.The structure and principle of 4 normal ESD devices are researched.In this thesis,the principles and demands of the ESD designing are proposed.Diode and SCR device are achieved based on 0.18 ?m CMOS technology.N+/P-well and P+/N-well diodes are chosen for the research of ESD robust and parasitic capacitance.The SCR devices include of the normal SCR,modified SCR and low-voltage triggering SCR.As the high trigger voltage of normal SCR,the modified SCR and low-voltage triggering SCR are used to lower the trigger voltage,but the parasitic capacitance is going large.Therefore,the trade-off of the trigger voltage and parasitic capacitance should be considered.Two low parasitic capacitance ESD devices are made out with 0.35?m SiGe process.One is the SiGe HBT,the parasitic capacitances are researched.The failure current of the SiGe HBT has reached 9 A by inserting collector contacts in the layout.The other is a novel self-triggered stack low capacitance SCR.The trigger voltage of this SCR would be unchanged while the number of stacks grows.However,the holding voltage would grow bigger with the growing of stacks.Due to the parasitic capacitance of this SCR is small,it is well used in strict ICs.Diode string and diode-triggered SCR are shown in this thesis with the experimental results in low voltage 55 nm RF CMOS technology.The layouts are researched for lower the parasitic capacitance.As we know,the robust of diode-triggered SCR is higher than that of diode string.But the SCR is hard to trigger because of the low resistance of wells in 55 nm process.Therefore,the active width of the well or appended trigger resistance is taken into account for triggering the SCR base on this process.