Co-Design Of RF ESD System Based On Optimization Of Parasitic Parameters

Electrostatic discharge(ESD)phenomenon become a current problem that restrict the safety and effectivity in integrated circuits.At present,designing of ESD protection system used in RF integrated circuits turns to hot topic and difficulty in the domain of ESD design.To producing an effective ESD protection level,specific ESD protection system is necessary to add in.However,there be a major difficulty in RF integrated circuits working at higher frequencies to providing ESD protection for the circuit:As the increasing of working frequency,the ESD protection network will inject parasitic parameter to interact with RF performance,the parasitic effects that introduced will further decline the performance of circuit.One side,the smaller of the ESD component size,the less parasitic capacitance inported;Besides,as the size of ESD protection component increased,the maximum failure current of device will ascend.Therefore,improving ESD-level or reducing deterioration of parasitic effect to the core circuit have the possibility of compromise optimization.For the co-design of RF-ESD systems,it is requisite to thoroughly consider the robustness,effectiveness,speed and transparency,so as to consider both RF application performance and ESD protection capability.The Part I is about ESD component model designing by exploring the equivalent discharge channel model of different device in ESD protection application.According to the interference of parasitic capacitance in RF system,it founds that the point of enhance the robustness of device is crucial.With multiple advantages like simple structure,low off-state leakage current,large on-state failure current,and low parasitic capacitance,diode is widely used in ESD protection circuits.Therefore,this paper optimizes parasitic parameters based on the standard diode structure model,design the parasitic PNP device structure of Psub-Cathode(N+)-Anode(P+)to design secondary discharge channel.The diode parasitic PNP structure designed in this paper extends the total discharge current channel under the bias condition of voltage clamp circuit,it means that the maximum failure current level(I_ESD)is improved without further deterioration of parasitic capacitance(C_ESD).The Part II is about the whole RF ESD system designing.It contains the design of the power clamp circuit triggered at suitable voltage,and design RF ESD co-design protection circuit for the IO port.For the power clamp circuit,a 5V voltage triggered power clamp circuit structure is designed with the working conditions of the foregoing device.The designed power clamp circuit can outfit an effective power clamp for the RF circuit system,and also supply a bias condition for the parasitic device to adapt to the ESD pulse.At last of this part has improved designed two kinds of RF ESD protection method circuits apply to the RF LNA instance,including two kinds of cooperative protection circuits for RF IO ports,called two-levels decay distributed network and multi-stage series protection circuit with parallel inductance.Compared with the traditional RF ESD co-design network,two-levels decay distributed network and multi-stage series protection circuit with parallel inductance put forward in this paper restrain the degradation of RF characteristics better in the low/high frequency conditions.In Part I,comparing with the classic diode device,the designed parasitic PNP device structure can significantly improve the maximum failure current by approximately 20%without introducing extra parasitic capacitance,and obviously enhance the robustness of device.In Part II,through apply the traditional cancellation network and two designed RF ESD co-design networks to an LNA circuit,the result indicates that the designed methods reduce effective RF performance degradation well while providing effective ESD protection,so that the designed circuits have better transparency in case of working frequency deviation.