| The pursue of high speed, high integration and large memory of information make the size of MOSFET scale down continuously, which results in this fact that some parameters who can be ignored in long-channel devices become more aggressively in short channel MOSFETs and then affect performances of the device. Therefore, many studies talked about how to maintain performances of long channel MOSFETs when the size of MOSFETs reduced. To reduce the short-channel effects, the measures like increasing channel doping concentration and reducing gate-oxide thickness is proposed. Then quantum effects on the devices performances should be considered due to the high doping concentration and the strong electric field. For a long time, the quantum effects in the accumulation and inversion layer are of significant concern. Nowadays, the infection of quantum effects of polycrystalline silicon is also investigated. Furthermore, the SDE(Source Drain Extension) structure has became the standard CMOS process which can restrain the hot carrier effects and short-channel effects effectively. Unfortunately, SDE would lead to the increase of parasitic resistances. Meanwhile, as the parasitic resistance cannot be reduced following the scaling down of MOSFETs, it causes the parasitic resistance accounting for a large proportion in the total resistance, and then the output characteristics and frequency characteristics are reduced.In this paper, the scaling down trend of MOSFETs and the great challenges for the process and physical mechanisms are introduced. And then the developments of MOSFETs structure, material and the process are discussed.To model the quantum effects in short channel MOSFETs, the quantum effects in the inversion layers is analyzed at first. Based on the approximation of triangular potential well, the schrodinger equation is solved and electron eigen energies and eigen wave functions can be obtained, then the carriers distribution in the inversion layers is given. According to this distribution, the expressions of surface capacitance and surface potential corresponding threshold voltage are presented. Then the influence of quantum effects in the inversion layers on the MOSFET threshold voltage and effective gate-capacitance are analyzed. Subsequently, analytical model of the quantum effects in polycrystalline silicon is presented, obtaining the carrier distribution and voltage drop in polycrystalline silicon. Through numerical simulation and figure fitting, the influence of quantum effects in polycrystalline silicon on MOSFETs threshold voltage and the influence of gate electrode capacitance on the effective gate-capacitance are researched.As the parasitic resistance cannot be reduced with the scaling down of MOSFETs, the influence of parasitic resistance on the MOSFETs performance shouldn't be neglected. To predict the parasitic resistance of the drain and source electrode precisely and analyze the relationship between the structure parameters and parasitic resistance, it is necessary to establish an effective parasitic resistance model. While analyzing the parasitic resistance, the parasitic resistance model of the long-channel and short-channel MOSFETs are introduced respectively, and the reason why the parasitic resistance model of short-channel MOSFETs exists great error is proposed when the Vg is lower. The reason can be ascribe to the calculation of the charge of accumulation layer. In the parasitic resistance model of short channel MOSFETs, the thickness of accumulation layer is assumed to zero, but the error is large at the low Vg. According to the results of analysis, the thickness of the accumulation layer cannot be assumed to zero and a new equation to solve the charge of the accumulation layer is given. The results show good accordance with actual parasitic resistance. At the end, the influences of device structure parameters on parasitic resistance are simulated and analyzed, which can be used in practical device design and improve device performances. |
PDF Full Text Request