The Research Of Three-dimension FinFET Gate-around Parasitic Effect And Model In Deep-Nanometer Process Technology

With the continuing progress of VLSI process technology,the three-dimension(3D)FinFET becomes the core device in IC,for its better gate-control ability,lower leakage and higher transistor density.However,3D structure and complex electric field distribution cause that the parasitic effect cannot be ignored any more.Therefore,it is significant to study the parasitic effect in 3D FinFET.With the TCAD simulation results,the analytical models of parasitic resistance and parasitic capacitance in deep-nanometer scaled 3D FinFET device have been built in this thesis.In addition,the related model coefficients have also been extracted.The major content in this thesis consists three parts as follow:1.With the reference of 3D FinFET structure in 14nm technology node,we have finished DC and AC simulation of 3D FinFET in TCAD.Based on the TCAD result data,the fundamental characteristic and performance have been discussed and analyzed,including threshold voltage,ratio of Ion and Ioff,sub threshold swing,DIBL and terminal capacitance.2.Model and extraction technology of 3D FinFET device.Considering the real 3D structure of device and TCAD simulation result,the parasitic resistance of FinFET have been divided as bias-independent parts,including raised source/drain region resistor Rcon and spreading resistor Rsp from fin to source/drain,and bias-dependent part called as source/drain extension resistor Rext.We successfully implement the separately extraction and modeling of these parasitic resistors.3.Modeling of 3D MOSFET parasitic capacitance with dual-k spacer structure.The coordinate conformal mapping method is adapted to deduce the model formula of dual-k dielectric vertical capacitor structure in our work.Then with the separation relation of capacitance in 3D device structure,the final model of FinFET total parasitic capacitance has been obtained.In the validation of dual-k vertical structure capacitor model,the statistical parameters between 5nm-45nm is introduced.The most of relative error between the proposed model and simulation are less than 10%.Moreover,the validation of 3D FinFET total parasitic capacitance model has the relative errors below 10%,with the various parameters of device,including Fin height,Fin width,Fin pitch,gate height,spacer thickness and spacer materials.Therefore,the proposed parasitic capacitance model is accurate and widely applicable.Finally,we embedded our capacitance model into SPICE model for circuit simulation.The fundamental delay performance of related inverter circuit and ring oscillator circuit has been discussed.