Modelling And Simulations Of Source/drain Parasitic Resistance And Capacitance In Nanoscale FinFETs

FinFET has become the mainstream technology because of its good channel control,lower power consumption and better scaling characteristics.However,due to the 3D characteristics of FinFET devices,the complexity and importance of their source/drain parasitic resistance and capacitance are gradually increasing with the continuous scaling of the device size.Therefore,a compact model that can describe the 3D characteristics of FinFET devices and the predictable parasitic capacitance and resistance of the drain source is of great importance for further device development and circuit development,and becomes a very urgent need.To solve the above problems,based on the 7 nm FinFET device,a compact model of the source/drain parasitic resistance and capacitance that can describe the 3D characteristics of FinFET device is established in this paper,and the model has a certain predictability for 5 nm or even 3 nm nodes.Synopsys'Sentaurus TCAD was used to verify the compact model.In this paper,a 7 nm FinFET TCAD model was constructed using the Sentaurus TCAD tool.The device structure of the model is based on the 7 nm Globalfoundries/Samsung process,and channel cross section electron density and potential distribution are calibrated the simulation results of Poisson Schrodinger quantum simulator.Based on this,the I_d-V_g curve of the device is calibrated with Globalfoundries/Samsung's 7 nm FinFET device,and the overall error is less than 5%.Then,from the point of view of device physics and according to the distribution of current,potential and electric field obtained from the TCAD simulation result,the existing position of the parasitic capacitance and resistance of the source/drain is analyzed,and the parasitic capacitance and resistance of the source/drain is divided into different modules.The resistance is mainly divided into four parts:the overlapping resistance R_ov,the Extension resistance R_ext,the epitaxial growth resistance R_epi and the Schottky contact resistance R_con.Capacitors are divided into external gate edge capacitance C_fg,o,internal gate edge capacitance C_fg,i,coincidence capacitance C_ov and PN junction C_j.Based on the results of the analysis,a compact model which can describe the 3D parasitic characteristics of FinFET is established.Finally,the extraction method of parasitic capacitance resistance based on TCAD simulation is used to extract the parasitic capacitance resistance value of source/drain from the TCAD simulation results,and the extracted value of TCAD simulation results is compared with the calculated value of the compact model in this paper.The results show that the maximum error between the calculated values of the compact model and the extracted values of the TCAD simulation results is less than 10%,and the overall error is less than 4%.In addition,the variation trend of the parasitic capacitance resistance of the drain source is analyzed from the perspective of the model,and the methods to reduce the parasitic effect are analyzed.