Design And Implementation Of A 2.5Gbps Clock Data Recovery Circuit For PCI Express

The demand on I/O bandwidth drives the conventional parallel bus to be replaced by the high-speed serial bus gradually. As one of the typical high-speed serial bus applications, the study on PCI Express is growing. Compared to the PLL, the input of CDR (Clock and Data Recovery) is high-speed random data, and the overall circuit works in a high speed input and high speed output status, all of this make the design of CDR difficult. Furthermore, CDR circuit is the key part to the PCI Express; its bandwidth directly determines the performance of the whole serial link system.In this thesis, the archtecture of the PCI Express and the related theory of clock data recovery and its small-signal and transient characteristics been researched deeply. Based on the theoretical analysis, a 2.5Gbps CDR has been designed and implemented.The contribution of this thesis includes:1. Designed and implemented a 2.5Gbps CDR using full-custom design method. The post-simulation result with Hspice shows that the design functions correctly and can fully meet the requirements of PCI Express.2. To overcome the disadvantage of traditional charge pump circuit, an improved charge pump circuit which has a better solution on the charge current overshort was designed.3. A differential voltage-controlled oscillator with high duty cycle, low jitter and wide working voltage range was designed and optimized.4 The layout design technique of high speed mix signal CDR circuit was studied; the layout post simulation shows that the technique works well.