The Research Of Parasitic Capacitance For MOSFET Which Is Based On The Semi-analytical Method

The extrinsic of MOSFET cause parasitic capacitance will affect the performance of the device, how to reduce the parasitic capacitance has been a hot topic to domestic and foreign scholars. The integration of integrated circuit always followed Moore’s Law and the MOS device size continue to shrink, so the gate oxide thickness of MOSFET requires to be much thinner, the reason is that the thin gate oxide thickness can improve the characteristics of MOSFET and can suppress the short-channel effects effectively. But the ultra-thin gate oxide thickness will cause a gate leakage current, besides the parasitic capacitance does not decrease with the decrease in proportion to the device size, so the high k dielectric which has low leakage current and thick physical thickness substitute SiO2as the gate material is needed. The previous parasitic capacitance model, with the conformal mapping method can only solve the parasitic capacitance of common MOSFET, the results used to the high k gate MOSFET directly require correction factor to correct the results. Semi-analytical method is the combination of analytical method and numerical method, it can obtain accurate expressions like analytical method, and also could be deal with complex boundary conditions flexibility like the numerical methods. The semi-analytical method of this paper is a combination of separation of variables method and rectangular equivalent source method.In this paper, we simplified the physical model of MOSFET by rectangular equivalent source method to obtain the gate-to-source definite solution of potential without any approximation. Then using the separation of variables method to solve the potential, and solving the unknown coefficients in the expressions of potential by the characteristic function expansion method. According to the Gauss’s law, the expressions of parasitic capacitances and the intrinsic capacitance can be obtained. Finally, the model validation and discussion is studied. The results show that the parasitic capacitances decrease with a decrease in the source length and the gate electrode thickness; as the gate oxide thickness decreases, the parasitic capacitances increase; the parasitic capacitances decrease as the gate dielectric constant increases; while as the channel length decrease, the parasitic capacitances do not change. Therefore, according to the results, the device designer can select the most appropriate parameters to design a MOSFET with the minimum parasitic capacitances. This paper presents the semi-analytical method to study parasitic capacitances of MOSFET without any approximation, the analytical expressions of capacitances with device parameters are obtained, so it can be used in the device design and circuit simulation program directly. The model has high precision, small calculation; it also can be used for both the common gate MOSFET and high-k gate MOSFET.