Study On The Key Technology Of Accurate Measurement For FF-level Capacitance On Wafer

With the technology nodes of Integrated Circuit constantly improving,parasitic capacitance and resistance brought by the device's gate structure and metal interconnect have become more and more serious.Parasitic effects have already become the key factors which restrict the frequency and power consumption of high-performance digital circuits.In order to make the EDA tool simulate the performance of the circuit accurately,the modeling and parasitic extraction of the SPICE model and the RC model in the Process Design Kit(PDK)should be based on the silicon data of the Testkey.With the feature size scaling down,the order of magnitude of the parasitic parameters on wafer also decreases,and the order of capacitance measurement reaches the f F-level.This leads to two kinds of problems:(1)Designing effective Testkeys and reasonable modeling schemes;(2)Accuracy of micro capacitance measurement on wafer.This paper studies the key technology of accurate measurement for f F-level capacitance on wafer.Two capacitance measurement methods were used,one is the Charge-based Capacitance Measurement(CBCM),and the other is the Ring Oscillatorbased Capacitance Voltage Measurement(RCVM).The measurement objects include the parasitic capacitance in MEOL/BEOL and the MOSFET C-V characteristics,and the results presented are from 22 nm Fully Depleted Silicon on Insulator(FDSOI)and28nm High-k Metal Gate(HKMG)technology node.The main research works are as follows:1)Based on the 22 nm FDSOI process,944 Testkeys of BEOL parasitic capacitance and 460 Testkeys of MEOL parasitic capacitance were designed.The Charge-injectioninduced-error-free(CIEF-CBCM)method was designed to measure these Testkeys.After the tape-out and test,the measurement results show that all kinds of Testkeys can be measured accurately by the CIEF-CBCM method,and the error between the CIEFCBCM method and the traditional LCR-meter measurement is less than 1%.2)Based on the 28 nm HKMG process,an improved CIEF-CBCM method and an improved Leakage and Parasitic-insensitive(LPI-CBCM)method were designed to measure the MOSFET C-V characteristics.Besides,an addressable design is introduced into the improved CIEF-CBCM circuit,which effectively reduces the layout area.After the tape-out and test,the results show that the two improved methods are both able to measure the C-V characteristics accurately.The RMS between the two methods is less than 3%,and RMS is less than 2% compared with LCR-meter.After normalization,the RMS between f F level capacitance and its corresponding large structure is less than 3%.3)Based on the 28 nm HKMG process,a novel addressable RCVM method was designed to measure the MOSFET C-V characteristics.After the tape-out and test,results show that the addressable RCVM method proposed can reach the accurate measurement of f F level capacitance.And this method not only reduces the layout area effectively,but also reduces the measurement error caused by process fluctuation through the design of multiple Testkeys sharing the same ring oscillator circuit.In conclusion,the CIEF-CBCM,LPI-CBCM and RCVM methods based on 22 nm FDSOI/28 nm HKMG process presented in this paper can measure the f F level capacitance on-chip accurately,and the accuracy of these methods reaches the sub-f Flevel.The research can provide an effective reference for the accurate measurement of micro capacitance on chip in advanced technology nodes.