Parasitic Capacitance Extraction And Fast Solver Study On VLSI

With the developing of Deep sub-micron technology,the effect of interconnecthas been one important factor influencing the device delay, power consuming andreliability. Therefore a fast and accurate interconnect extraction tool is important atthe design field of VLSI.The first main content of the paper is about the coupling of BEM (boundaryelement method) and FDM (finite difference method) on 3-D capacitance extraction.The reason of producing this assume is that sometime the error is pretty severity whenprocessing some empty medium in which there is no conductor with BEM alone. Thispaper produces some arithmetic and discusses them in detail. In the end, implement anarithmetic to the B3D system, a software to extract 3-D capacitance.The second main content of the paper is about a preconditioned method. With theever-increasing density of integrated circuits, the need for speed of parameterextraction becomes more and more crucial. This paper use boundary element methodto extraction interconnect capacitance, modify an existing preconditioned method andapply it to practical computation. The theoretical analysis and numerical results of twotypical examples show that this method can decrease the numbers of iterative by 30%and reduce the computation time greatly.