Study On Parasitic Capacitance Extraction Algorithm For Interconnected Circuits Considering Suspended Dummy

With the rapid increase of the signal frequency and the decrease of the feature size of VLSI, more and more physical effects, which make little sense in the early development of integrated circuits, are playing a much more important role on restricting the development of IC performance. As one of the representative factors, the parasitic effect of interconnect makes the issue of signal delay and signal integrity become more and more serious, and it could even affect the normal work of the circuits.At the same time, in order to resolve the planarity problem caught by chemical mechanical polishing process, dummy fills are extensively inserted into circuits. However, the presence of dummy fills not only has a significant impact on the value of interconnect capacitance, but also puts forward a new challenge for the conventional parasitic capacitance extraction algorithms. How to rapidly and accurately extract parasitic capacitance of circuits including large amount of dummy fills has become an important issue in the field of Compute-Aided-Design(CAD), which has a significant implications for the improvement of integrated circuit performance and yield.Aiming at the parasitic capacitance extraction for the circuits including dummy fills, a hierarchical algorithm based on floating random walk algorithm is proposed. First, with the application of domain decomposition technique, separate the domain including dummy fills from the orininal circuits, and divide the domain into several sub domains according to the regional distribution characteristics of dummy unit. Second, the markov transition matrix of the sub domain which has standard structure is established. At last, a novel random walk algorithm based on the transfer probability is proposed, which breaks up the conventional floating random walk procedure into3subprocedures------the probability transfer process occurring within dummy areas, the floating random walk process occurring within dummy areas and the floating random walk process occurring within outer region.When calculating the parasitic capacitance matrix, our method could not only utilize the regional distribution characteristics of dummy array, but also could set up macro model based on the standard dummy structures, which could increase the reuse rate of data. The experimental results show that, compared with conventional algorithm based on FRW, our method exhibits lower computational cost and the same accuracy is guaranteed.