Research And Design Of A 16-bit 100 MS/s Sha-less Pipeline ADC

High performance ADCs of high speed, high precision and low power are becoming increasingly important with the rapid development of global wireless communications, radar and other information systems. The SHA-less pipeline ADC, however, is the better choice to realize the high speed, high precision and low power consumption in the various type of ADCs. The architecture of high speed and high precision pipeline ADC and some key circuits were researched and designed deeply, and a 16-bit 100 MS/s SHA- less pipeline ADC based on 0.18 μm CMOS process was proposed in this thesis.Firstly, in order to get a architecture with lower power consumption, this paper analyses some non- ideal factors of pipeline ADC that affect the system performance, including the capacitor mismatch, noise, the finite dc open- loop gain and finite unity gain bandwidth of op-amp. And then, the systematic precision distribution with lower power consumption of ADC was determined in consideration of 0.18 μm CMOS process, power consumption of key modules and the capacitance reduction(scaling down).Secondly, a technique which has the wider digital correction range of comparator offset and relaxes the timing matching requirement between the Sub-ADC and MDAC sampling networks by reducing the gain of 3.5-bit front-end multiplying digital to analog converter(MDAC) from 8 to 4 is adopted in view of sampling error between the MDAC and the Sub-ADC which caused by removing the dedicated front-end sample-and-hold amplifier(SHA). Meanwhile, the structure of the second stage MDAC and the redundant signed digit(RSD) calibration algorithm were also modified. In addition, based on the error caused by capacitor mismatch, the non-monotonic of system caused by capacitance mismatch was corrected through a foreground correction technique.Thirdly, in terms of requirements of the system, some key modules, like bootstrapped switch, MDAC and comparator, were implemented on 0.18 μm CMOS process. In order to achieve high gain and high bandwidth, the operational amplifier of first stage MCAC was adopted as two-stage gain-boosted and Miller compensated structure.Finally, the layout of some key circuits and entire pipeline ADC were accomplished and post-simulated on 0.18 μm CMOS process. And the post-simulation results show that the ADC sampling a 10.15625 MHz input at 100 MS/s and achieves an SNDR of 90.3 d B, an SFDR of 103.6 d B and an ENOB of 14.7 bit. The ADC has an SNDR of greater than 80 d B and has an SFDR of greater than 85 d B up to 47 MHz input signals. Moreover, The ADC consumes 680 mW from a 3.3 V supply, and the area of layout is 48 mm2.