The Key Research Of 12 Bit High Speed Mixture Structure A/D Converter

As the development of integrated circuit process,portable devices are beginning to be widely used.Electronic devices gradually have a tendency of portability,miniaturization and low power consumption.In the field of wireless communication,image and video,the performance requirements of analog to digital converter(ADC)are also gradually improved.High speed,high resolution and low power have been the main challenge and requirement of ADC design.SAR ADC has been popular in middle/high resolution area because of the character of simple circuit structure and low power consumption.But due to its capacitor array increasing exponentially as resolution increase,resulting in a very low speed in high resolution area,this greatly restrict application of SAR ADC.However,pipeline ADC has been widely used in high resolution area because it has a good compromise among speed,resolution and power.But pipeline ADC still has disadvantages that consume large power and area because of complex circuit structure and containing high gain and bandwidth operational amplifier.With the development of technology in emerging field,traditional ADC structures have not fully met the requirement of the system,at the background of increasingly difficult to put forward to the new revolutionary structure,the study of hybrid structures has become critical and it is relatively easy to implement.Pipeline SAR ADC is a new structure that combines pipeline ADC and SAR ADC,it has made some improvements on the traditional pipeline ADC circuit and combined SAR ADC,so there is a better compromise on circuit performance,which has been widely studied.In this thesis,the overall structure and principle of the pipeline SAR ADC and MDAC of pipeline ADC are introduced firstly,then introduce a new circuit structure called pipeline SAR ADC which combines pipeline ADC and SAR ADC.Moreover,non-ideal factors are analyzed in detail and put up with the solution.A new circuit timing scheme was introduced in the key circuit module,which further decrease the power consumption of each stage.Using dynamic residue amplifier with cascoded integrator and common-mode detect to replace traditional amplifier which has a better compromise among speed,resolution and power.Through analysis and experiment,it can be found that Pipeline SAR ADC improves performance compared with traditional structure,and it is a new method to design high resolution,high speed and low power consumption ADC.The prototype was fabricated in TSMC 65 nm CMOS technology to achieve 100MS/s 12 bit ADC.The proposed ADC is a two-stage pipeline ADC,the first stage is a 6 bit MDAC,the second stage is a 7 bit SAR.It achieves 12 b resolution by redundancy digital error correction method.The post-layout simulation results show that the ADC achieves 90.6d B SFDR and 69.7d B SNDR with Nyquist input at 100MS/s.the DNL is within+0.75LSB/-0.75 LSB and the INL is within +1.5LSB/-1.5LSB.The experiments found that measurement results fit in with post-simulation results.