The Design Of High-speed And High-resolution Pipeline A/D Converter

A/D converter, As an analog signal and digital signal connection link, plays an important role in date conversion. Compared with other types of A/D converter,pipeline A/D converter can have a good compromise in power, area, speed and resolution, which makes it become the preferred structure to realize high speed and high resolution A/D converter. With lower and lower supply voltage, smaller and smaller device dimension, the desin of high gain operational amplifer is becoming more and more difficult, while the gain of operational amplifer derectly dertermines the performance of pipeline A/D converter in ther very great degree. Therefore, the design of high speed and high resolution pipeline A/D converter is a severe challenge.The thesis first briefly introduces the basic concepts of pipeline A/D converter and its work process. Then by analyzing the working principle of front-end sample and hold circuit, MDAC circuit, and sub-ADC circuit, a detailed error analysis in pipeline ADCs is proposed, which mainly includes noise, switch error, Settling time error, capacitor mismatch and the offset voltage of comparators. Furthermore, The ADC parameters are analyzed and optimized surrounded noise, power consumption, and linearity. For noise, the expression of the equivalent input noise power is deduced; for power consumption, scaling down technique and the number of the comparator optimal algorithm is proposed; and for linearity, this thesis focuses on the relation of linearity and the first stage resolution. Finally, a 13 bit 40 MSPS pipeline A/D converter is completed based on SMIC 0.35μm 2P3 M mixed CMOS process.Simulation results show that under 3V supply voltage, the power consumption of the circuit is 142 m W. When the sampling clock at 40 MHz and the input signal at 9.9609375 MHz, the SNDR, SFDR and ENOB of first stage MDAC is about 84.52 dB, 86.6dB, and 13.75 bit, respectively; the bootstrapped switch, they are about 84.1dB, 85.19 dB, and 13.67 bit, respectively; the ADC, they are about 70.48 dB, 77.92 dB, and 11.41 bit. These performances meet the requirements of the 13 bit 40MSPS pipeline ADC. The chip effective area is 1700×800μm2.