Design Of Operational Amplifiers For High-speed High-resolution Pipeline ADC

Since Jack Kilby at Texas Instruments introduced the first integrated circuit(IC) in 1958, a new industry was born. In the past 50 years, electronic products using IC chip emerged in endlessly. With the progress of the times, people on the performance requirements of electronic products is increasing, which means a higher demand of the performance of IC chip. Operational amplifier(Op-amp) is an important basic unit of digital-analog hybrid system, its design and optimization is a very important research topic.Analog to digital converter(ADC), which is the bridge to connect analog and digital systems, becomes more and more important. Pipeline ADC is usually chosen as a high-speed high-precision candidate because it has good tradeoff between speed, power and chip area. In pipeline ADC circuit configuration, Op-amp is one of the core modules, and its design has a direct impact on the performance of pipeline ADC.As a result, the research and design of high gain, wide bandwidth Op-amp for high-speed high-precision pipelined ADC is essential.In this thesis, a two-stage fully differential Op-amp applied to pipeline ADC was first designed. In the first stage, a folded cascode structure is used, while in the second stage, a simple common-source structure is used. In order to stabilize the output common-mode voltage, both of these two stages have common-mode negative feedback circuit. In addition, in the first stage a simple but effective cross-coupled negative feedback structure is used. The Op-amp was designed and laid out using CMOS 0.18μm technology. Simulation results show that the DC gain of the design Op-amp reaches 92.8 d B, and unity-gain bandwidth(GBW) is 195.5 MHz. Printed circuit board was also designed and fabricated to support chip test. Test results show that the DC gain of the design Op-amp reaches 83 d B, and GBW is 170 MHz.A second Op-amp was introduced for a 14 bit 100MS/s pipeline ADC. This Op-amp uses the Gain-boosting structure, using this technique does not change the DC operational state of the circuit, and it greatly improves the gain of the Op-amp.The Op-amp design was also implemented in CMOS 0.18μm technology. Simulation results show that the DC gain of the design Op-amp reaches 100.6 d B, and GBW is 986.9 MHz.