Reseach And Design Of Fractional-n Pll For MICS

With the rapid growth of the wireless communications market, the demand for low-cost high-performance radio frequency integrated circuits has become increasingly urgent. While the rapid development of the semiconductor industry but also for all communications module integrated on a single chip may be provided. Among them, the most difficult is to provide integrated local oscillator signal is phase-locked loop. Since the phase noise of the PLL phase noise is difficult to meet the needs of the wireless communication system. Therefore, the study of a variety of phase-locked loop is also increasing. From integer to the fractional frequency divider, from analog to digital, PLL’s performance continues to be enhanced, while costs continue to be reduced.Receiver frequency synthesizer as a key module, which directly determines the performance and accuracy of the oscillator signal purity. Since the integer-N PLL reference frequency of the receiver channel width, and the PLL loop bandwidth is less than one tenth of its reference frequency. Thus, the integer-N PLL is difficult to meet MICS receiver to quickly lock, high-resolution requirements. Therefore, the paper designed frequency synthesizer uses a fractional-N phase-locked loop structure.The text from the basic unit module to the system architecture for fractional PLL carried out a detailed theoretical analysis. On the basis of theoretical analysis, the design of a wireless transceiver system for MICS 400 MHz ~ 430 MHz low-power fractional charge pump phase-locked loop. Which VCO using fourth-order differential structure of the ring oscillator, divider using six pulse swallow programmable divider, modulator using MASH1-1-1 structure, the charge pump uses a charge pump with a mirror branch and voltage follower to eliminate charge sharing, loop filter filter uses a passive RC filter.The paper first receiver system according to MICS indicators planned fractional PLL modules index, and use MATLAB / Simulink modeling to verify the reasonableness of the indicators planning. Secondly, under the Cadence Spectre platform to complete fractional PLL design simulation. Again, depending on the design of the circuit to complete the layout in Cadence Virtusoo, the total area of the PLL chip layout designed for 0.8mm * 1.2mm(including PAD). After the simulation, fractional PLL operating voltage of 1.8V, the output frequency range: 400 MHz ~ 430 MHz, the channel width of 300 kHz, the lock time is less than 25 us, fractional spurs less than-50 dBc, phase noise is-104dBc/Hz @ 1MHz. PLL designed to meet the performance requirements of the radio receiver MICS. The fractional-N PLL chip technology in GSMC0.18 um nasty piece using QFN24 pin package. When testing, VCO output frequency range is 95 MHz ~ 741.7MHz, phase noise is-91.47dBc/Hz @ 1MHz. Divider can work, but the entire phase-locked loop can not be locked. After the face of this design gave a detailed summary, and the corresponding improvement measures.