.10 Bits, 200mhz Segmented Current-steering Dac Design

With the fast development of computer technology,digital processing technology and microelectronic technology,advantaged video systems are presented continually.This paper has given the basic design principle and architecture of high speed and low dissipation of DAC. A 10bits,200MHz segmented current-steering DAC is designed with the top-down method,which can be applied to the video conversion system. High speed and low dissipation are reached.The traditional DAC is classified into three sorts by scaling mode. They are voltage scaling,current scaling and charge scaling. By compare,current scaling DAC is the most fast and occupies the least area. The current-steering structure is a type of improved current scaling structure. The segmented current-steering has good linearity and occupies small area,so it is widely used in high speed DAC. Segmented structure with"5+5"is adopted. Comparing"5+5"with"8+2"by analyses and simulation, though"5+5"sacrifices some performance of DNL, it occupies smaller area. The DNL which is within±2LSB satisfies requirement of video process. Current-source matrix of"8+2"structure is large, it occupies large area. Taking it all round, the author attempted to use"5+5"segmented structure. The designed DAC consists of many sub-circuits. They are VREF,IREF,current matrix,switch matrix,latch and decoder. VREF,Current matrix,switch matrix and decoder are the key parts in DAC design. The errors caused by them are analyzed and suppressed in the paper. Many kinds of simulation tools have been used in this design process,and some very high accuracy DNL &INL simulation results have been captured by a very smart method.The DAC is fabricated in 0.18um standard digital CMOS process and simulated by CADENCE and HSPICE. Verilog,VerilogA,Matlab and nanosim are also used in this paper. After pre-simulation is finished,layout is designed and post-simulation net-list is abstracted.to make sure the results of post-simulation correct. The DAC is then taped out. The paper has achieved a DAC with 10bit resolution,200MHz conversion rate,92mW dissipation and 0.577mm~2 area.