Research And Design Of 8-bit High Speed DAC

Rapidly developing technologies such as computers,digital signals,and integrated circuits are increasingly demanding the performance of digital-to-analog converters(DAC).The conversion speed of DAC,which connects digital signals and analog signals,has become one of the bottlenecks restricting the high-speed development of communication system.Therefore,it is of great practical significance and broad application prospects to research and design high-speed DAC with independent intellectual property rights.In this thesis,an 8 bits high speed current steering DAC with “4+4” segmented full thermometer decoding is designed based on IBM 0.13?m BiCMOS process.Firstly,we describe the basic principle,performance parameters,and the common basic structure of DAC.Through the analysis and comparison of the performances of the three structures,the current steering configuration of 8-bit “4+4” segmented full thermometer decoding structure is determined,which combines the advantages of good linearity and small outer part.Secondly,by analyzing factors influencing the performance of DAC,it is concluded that the main factors that affect the static and dynamic performance of DAC are the matching error and the magnitude of finite output impedance in the current source,and the selection of the decoding method,which provides theoretical support for the subsequent-up circuit design.Thirdly,the systematic design of the DAC circuit is carried out,including the design of digital circuit and artificial circuit.The artificial circuit part mainly covers the circuits of band-gap voltage reference,voltage to current bias circuit,current source gate voltage generation circuit,and the current source-level switch tube.While the digital part mainly contains the circuits of input register,clock driver,thermometer decoder,and the switch driving waveform generation circuit.During the process of circuit design,the optimization focuses on the performances of the current source design and the switch driving waveform.The size of the current source is determined by the relations between the size and precision of the current source;the output impedance of the current source is improved by using the common source common gate current source structure;and the gradient error of the current source layout is reduced by adopting the hierarchical symmetrical switch sequence.The switch driving waveform is designed to reduce the output signal burr and increase the speed of the circuit by adding the output of the limiting circuit.Finally,the whole circuit design is debugged and simulated repeatedly.The schematic design,layout design and post-simulation verification of the DAC chip are completed in this thesis,with the overall area of the layout of 775?m×745?m.The simulation of the designed DAC circuit shows that the circuit can work stably at the sampling frequency of 8GHz with good static and dynamic characteristics.Under the 1.5V power supply voltage,the power consumption is 54.79mW;the DNL is less than 0.1LSB;and the INL is less than 1LSB.Under the 8GHz clock sampling frequency and 3.95 GHz output signal frequency,the SFDR is 37.4dB.The current-steering DAC with segmented full thermometer decoding design adopted in this thesis is of great significance to the future design and application of the high speed DAC.