Design Of High Speed Segmented Current Steering D/A Converter

High speed digital-to-analog converters(DAC;Digital-to-Analog)have been widely used in high-resolution video/image signal processing,digital acquisition and communication systems,direct digital signal synthesis,radar imaging systems and other fields.Social development has promoted the demand for higher data rate processing and the demand for excellent performance DAC in the market is becoming more and more urgent.With the maturity of high-frequency communication technology,digital-to-analog converters are gradually developing towards the RF side,which greatly simplifies the design of the entire system and it has broad application prospects in military equipment and civilian consumer electronics.This paper has completed the design of the main circuit modules of DAC,such as data synthesis circuit,reference circuit,bias circuit,switching current source unit and its array arrangement,switching drive circuit and DLL circuit,in a 16-bit 2.5GS/s sampling rate current-steering digital-to-analog converter.Based on the error analysis of the piecewise DAC system,a piecewise structure of 5+4+7 is adopted to achieve a good balance among the complexity of decoding,circuit area and system performance.In order to make the decoding circuit have a faster decoding speed,the decoding mode of queue decoding is adopted.The layout of the main module circuit is explained,and the binary tree layout is adopted for the power cord and the clock.Finally,the system circuit is simulated,the test scheme of the real circuit is given,and the circuit test is completed.The DAC circuit designed in this paper is based on 65 nm CMOS technology,the power supply voltage is 3.3V/1.2V,the differential current output mode is adopted,and the designed output current is 20 m A.The simulation value of DNL is less than±0.61 LSB,and the simulation value of INL is less than ±1.5LSB.The setup time of up jump and down jump is 9.55 ns and 9.58 ns at full-scale startup.Through the test of the prototype circuit,the SFDR value is 72.42 d BC and 45.97 d BC when the input signal is16.987 MHz and 257.692 MHz at the sampling rate of 2.5GS/s,and the third-order intermodulation distortion is 60.19 d BC when the input two-tone signal is 119 MHz and120MHz.