The Design Of High-speed High-precision DAC

With the rapid development of the computer field、the signal processing field、 integrated circuits field, the performance of communication system become increasingly high. And digital-to-analog converter is important member of the communication system. It’s accuracy and speed directly affects the accuracy and speed of communication system, it has a significant impact to developments of the signal processing and computer field. In recent years, the domestic investment become bigger in the field of DAC.I complete the following digital-to-analog converter design based on the environment.This paper analyzes the basic structure of the DAC:according to the way of zoom, DAC can be divided into:charge scaling, voltage scaling and current scaling. Through analysis the advantages and disadvantages of the three structures, I select the current scaling. The paper applies the segmented current steering structure which combines the advantages of better linearity and a smaller area. Firstly, the paper analysis and compare the chip area、complexity and performance of the different segmented current steering structure, then select5+4+5segment way which can reach the optimum combination of thermometer and binary weighted current source. In addition, the paper build the non-ideal model of DAC and simply analysis impact of the current source mismatch、the finite output impedance、the circuit noise and the non-ideal DAC performance in order to guide the design of DAC circuit based on Verilog-A language.In this paper, through analysis the DAC error model, I choice the way of optimized circuit structure and circuit size to reduce impact of a variety of non-ideal factors on the DAC. This article design a high performance bandage reference circuit to provide the stable voltage for DAC, to ensure that the unit current source can be process-insensitive and temperature-insensitive。Based on SMIC0.18um CMOS process, the paper complete the DAC design。Through Appling some EDA software:cadence、verilog-XL、matlab, I simulate the DAC circuit。 After testing, the SFDR can reach90dB@1MHz, INL/DNL>1.5LSB。...