Research And Design On Frequency Synthesizer Of UHF RFID Application In130nm CMOS

Radio frequency identification(RFID) technology improves the accuracy and timeliness of information about the movement of goods in supply chains because of its large information storage size and merits on fast track of bulk goods logistics without direct contact and has moved from obscurity into research hotspot. On the other hand, as CMOS technology steps into nano-meter era, highly integrated system-on-chip(SOC) is the mainstream of circuit design, thus bringing huge research and market potential for RFID reader chips.Frequency synthesizer, which provides local oscillation signals for RFID reader chips, is the key circuit accounting for RFID reader chips’ performance. Circuit designs of voltage controlled oscillator and charge pump are the main difficulties. This thesis aims at the design of frequency synthesizer circuits in RFID reader chips that apply to Chinese mainland UHF RFID standards. A dual loop integer-N phase locked loop(PLL) is implemented in3.3V/1.8V130nm CMOS technology with careful analysis and tape-out or post-layout simulation verification on the design method and parameter preference principles in PLL’s sub circuit blocks.Voltage controlled oscillator(VCO) determines in-band noise level and power consumption of PLL and is the base of high quality PLL design. Ring VCOs and LC VCOs are the two mainstream type of CMOS VCOs. The thesis seeks for the best noise performance of VCOs with minimum power consumption. Based on noise analysis of differential delay cell in ring VCOs, design principles for MOS device sizing and load type selection in delay cell are demonstrated with tape-out verification. Optimization methods of low noise LC-VCOs are investigated and verified with post-layout simulation results on5aspects, respectively inductors, varactors, cap arrays, cross coupled MOS devices and biased tail current source.In frequency synthesis, charge pump is the dominant block that determines the level of the unwanted FM modulation causing the reference spur. Low power charge pump with minimum reference spur decides circuit optimization directions. Non-ideal effect of the charge pump is carefully considered with corresponding mathematical models in this thesis and a5-bit tail current controlled charge pump is presented, achieving reference spur level of below-88dBc. Digital circuit blocks, referring mainly to phase frequency detector(PFD) and dividers, are also addressed. Based on different working frequencies of the dividers, true type single-phase clock(TSPC) triggers and current logic type(CML)triggers are compared and applied to3different divider circuits with layout and post-layout simulation results.