Research And Design Of Millimeter Wave Band Phase-Locked Loop Based On CMOS Process

With the development and maturity of wireless communication,the phase-locked loop(PLL)has become a hot research topic in recent years as an important module that can generate stable clock signals and be used for closed-loop tracking circuits.Millimeter wave has a wide bandwidth,the beam is narrow,and the theoretical size of millimeter wave devices is smaller,attracting scientists from all over the world to expand the application range;after years of optimization and iteration,the CMOS process is constantly shrinking in feature size,performs well at higher frequencies,and has more obvious advantages in terms of cost and integration compared to other processes,gradually becoming the mainstream process for commercial millimeter-wave integrated circuits.Therefore,designing a millimeter-wave PLL based on the CMOS process has significant practical significance.In this thesis,the theory of PLL is analyzed in depth.A Type II PLL structure is adopted,mainly including a phase-frequency detector(PFD),charge pump(CP),low-pass filter(LPF),voltage-controlled oscillator(VCO),and integer frequency divider.Based on the initial setting of loop parameters,its Behavioral-Level Simulation is carried out in MATLAB to determine its loop stability.In the circuit structure of this thesis,the VCO adopts the NMOS-PMOS cross-coupling structure design,introduces and designs a 3-bit variable capacitor module.By controlling the potential,the VCO output signal frequency can be changed.The simulation shows that the output signal frequency tuning bandwidth is about 3 GHz,its phase noise is-105.08 d Bc/Hz@1MHz,and its power consumption is 6.22 m W.A frequency divider chain is designed,which consists of two stages of CML frequency dividers and continuous digital frequency dividers.The continuous digital frequency divider can achieve continuous division of 16-31.A PFD which eliminates the dead zone by introducing delay elements and a charge pump with good current matching performance and high output signal linearity are designed.The current mismatch is less than 1%.The output current noise is-222.99 d B when the two modules are cascaded.A third-order passive LPF is used to filter the noise of the charge pump output signal.Based on the design of the above modules,the overall circuit of the PLL is built on the hlmc40LP CMOS process,and the layout area size is 726.96*604.60μm~2.The simulation results show that the circuit can operate normally,and the output frequency can cover the 24 GHz band.The locking time is short and the jitter is small.The phase noise is calculated to be-99.65 d Bc/Hz@1MHz in MATLAB.